DATASHEET ISL6548A FN9189 Rev 2.00 ACPI Regulator/Controller for Dual Channel DDR Memory Systems January 3, 2006 The ISL6548A provides a complete ACPI compliant power Features solution for up to 4 DIMM dual channel DDR/DDR2 Memory Generates 5 Regulated Voltages systems. Included are both a synchronous buck controller to - Synchronous Buck PWM Controller for DDR V DDQ supply V during S0/S1 and S3 states. During S0/S1 DDQ - 3A Integrated Sink/Source Linear Regulator with state, a fully integrated sink-source regulator generates an Accurate V /2 Divider Reference for DDR V DDQ TT accurate (V /2) high current V voltage without the DDQ TT - PWM Regulator for GMCH Core need for a negative supply. A second PWM controller, which - Sink/Source LDO Regulator for CPU/GMCH V requires external MOSFET drivers, is available for regulation TT Termination of the GMCH Core voltage. A sink/source LDO controller is - LDO Regulator for ICH7 also integrated for the CPU/GMCH V termination voltage TT regulation. Another LDO is available for the ICH7 voltage. ACPI Compliant Sleep State Control The switching PWM controller drives two N-Channel Glitch-free Transitions During State Changes MOSFETs in a synchronous-rectified buck converter V PWM Controller Drives Low Cost N-Channel DDQ topology. The synchronous buck converter uses voltage- MOSFETs mode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of 250kHz Constant Frequency Operation 2% over line, load, and temperature ranges. The output is - Both PWM Controllers are Phase Shifted 180 user-adjustable by means of external resistors down to 0.8V. Tight Output Voltage Regulation An integrated soft-start feature brings all outputs into - All Outputs: 2% Over Temperature regulation in a controlled manner when returning to S0/S1 Fully-Adjustable Outputs with Wide Voltage Range: Down state from any sleep state. During S0 the VIDPGD signal to 0.8V supports DDR and DDR2 Specifications indicates that the GMCH and CPU V termination voltage TT Simple Single-Loop Voltage-Mode PWM Control Design is within spec and operational. Fast PWM Converter Transient Response All outputs, except V , have undervoltage protection. The ICH7 switching regulator also has overvoltage and overcurrent Under and Overvoltage Monitoring protection. Thermal shutdown is integrated. OCP on the V Switching Regulator DDQ Integrated Thermal Shutdown Protection Pb-Free Plus Anneal Available (RoHS Compliant) Applications Single and Dual Channel DDR Memory Power Systems in ACPI Compliant PCs Graphics Cards - GPU and Memory Supplies ASIC Power Supplies Embedded Processor and I/O Supplies DSP Supplies FN9189 Rev 2.00 Page 1 of 16 January 3, 2006ISL6548A Pinout Ordering Information ISL6548A (QFN) TEMP. TOP VIEW PART PART RANGE PKG. NUMBER MARKING (C) PACKAGE DWG. ISL6548ACRZA ISL6548ACRZ 0 to 70 28 Ld 6x6 QFN L28.6x6 (Note) (Pb-free) 28 27 26 25 24 23 22 ISL6548ACRZA-T ISL6548ACRZ 0 to 70 28 Ld 6x6 QFN L28.6x6 1 21 5VSBY DRIVE3 (Note) (Pb-free) Tape and Reel S3 2 20 FB3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free 3 19 P12V PWM4 material sets molding compounds/die attach materials and 100% matte GND tin plate termination finish, which are RoHS compliant and compatible GND 4 18 FB4 29 with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that DDR VTT 5 17 COMP4 meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. DDR VTT 6 16 COMP VDDQ 7 15 FB 89 10 11 12 13 14 FN9189 Rev 2.00 Page 2 of 16 January 3, 2006 VDDQ LGATE DDR VTTSNS GND DRIVE2 U UGATE FB2 BOOT VIDPGD PHASE DRIVE2 L S5 VREF IN OCSET