DATASHEET ISL6754 FN6754 Rev 2.00 ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control June 2, 2016 The ISL6754 is a high performance extension of the Intersil Features family of Zero-Voltage Switching (ZVS) full-bridge PWM Adjustable resonant delay for ZVS operation controllers. Like the ISL6752, it achieves ZVS operation by driving the upper bridge FETs at a fixed 50% duty cycle while Synchronous rectifier control outputs with adjustable the lower bridge FETs are trailing-edge modulated with delay/advance adjustable resonant switching delays. Voltage- or current-mode control Adding to the ISL6752s feature set are average current 3% current limit threshold monitoring and soft-start. The average current signal may be Adjustable average current limit used for average current limiting, current sharing circuits and average current mode control. Additionally, the ISL6754 Adjustable dead time control supports both voltage- and current-mode control. 175A start-up current The ISL6754 features complemented PWM outputs for Supply UVLO Synchronous Rectifier (SR) control. The complemented Adjustable oscillator frequency up to 2MHz outputs may be dynamically advanced or delayed relative to the PWM outputs using an external control voltage. Internal over-temperature protection Buffered oscillator sawtooth output This advanced BiCMOS design features precision dead time and resonant delay control, and an oscillator adjustable to Fast current sense to output delay 2MHz operating frequency. Additionally, multi-pulse Adjustable cycle-by-cycle peak current limit suppression ensures alternating output pulses at low duty 70ns leading edge blanking cycles where pulse skipping may occur. Multi-pulse suppression Applications Pb-free (RoHS compliant) ZVS full-bridge converters Related Literature Telecom and datacom power AN1603, ISL6752/54EVAL1Z ZVS DC/DC Power Supply Wireless base station power with Synchronous Rectifiers User Guide File server power AN1619, Designing with ISL6752DBEVAL1Z and Industrial power systems ISL6754DBEVAL1Z Control Cards Pin Configuration ISL6754 (20 LD QSOP) TOP VIEW VREF 1 20 SS 2 19 VADJ VERR CTBUF 3 18 VDD 4 17 RTD OUTLL RESDEL 5 16 OUTLR 6 15 CT OUTUL FB 7 14 OUTUR RAMP 8 13 OUTLLN CS 9 12 OUTLRN IOUT 10 11 GND FN6754 Rev 2.00 Page 1 of 20 June 2, 2016ISL6754 Ordering Information PART NUMBER PACKAGE PKG. (Notes 1, 2, 3) PART MARKING TEMP. RANGE (C) (RoHS Compliant) DWG. ISL6754AAZA 6754 AAZ -40 to +105 20 Ld QSOP M20.15 ISL6752/54EVAL1Z Evaluation Board ISL6754DBEVAL1Z ISL6754 Evaluation Daughter Board NOTES: 1. Add -T suffix for 2.5k unit tape and reel option. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6754. For more information on MSL, please see tech brief TB363. Pin Descriptions PIN PIN NUMBER NAME DESCRIPTION 1 VREF The 5.00V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a 0.1F to 2.2F low ESR capacitor. 2 VERR The control voltage input to the inverting input of the PWM comparator. The output of an external Error Amplifier (EA) is applied to this input, either directly or through an opto-coupler, for closed loop regulation. VERR has a nominal 1mA pull-up current source. When VERR is driven by an opto-coupler or other current source device, a pull-up resistor from VREF is required to linearize the gain. Generally, a pull-up resistor on the order of 5k is acceptable. 3 CTBUF CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing 2mA. It is offset from ground by 0.40V and has a nominal valley-to-peak gain of 2. It may be used for slope compensation. 4 RTD This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this pin and GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the resistor current. The PWM dead time is determined by the timing capacitor discharge duration. The voltage at RTD is nominally 2.00V. 5 RESDEL Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower FETs. The voltage applied to RESDEL determines when the upper FETs switch relative to a lower FET turning on. Varying the control voltage from 0V to 2.00V increases the resonant delay duration from 0 to 100% of the dead time. The control voltage divided by 2 represents the percent of the dead time equal to the resonant delay. In practice the maximum resonant delay must be set lower than 2.00V to ensure that the lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs. 6 CT The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200A current source and discharged with a user adjustable current source controlled by RTD. 7 FB FB is the inverting inputs to the Error Amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or used as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded. 8 RAMP This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected to CS and the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate an appropriate signal, RAMP may be connected to the input voltage through a RC network for voltage feed forward control, or RAMP may be connected to VREF through a RC network to produce the desired sawtooth waveform. 9 CS This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1.00V nominal. The CS pin is shorted to GND at the termination of either PWM output. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. This delay may result in CS being discharged prior to the power switching device being turned off. 10 IOUT Output of the 4X buffer amplifier of the sample and hold circuitry that captures and averages the CS signal. 11 GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. FN6754 Rev 2.00 Page 2 of 20 June 2, 2016