ISL78302AR1AZ-T7A Renesas

DATASHEET ISL78302 FN7696 Rev 6.00 Dual LDO with Low Noise, High Performance and Low IQ November 6, 2014 ISL78302 is a high performance dual LDO capable of sourcing Features 300mA current from each output. It has a low standby current Integrates two 300mA high performance LDOs and is stable with an output capacitance of 1F to 10F and an ESR of up to 200m. Excellent transient response to large current steps The device integrates an individual Power-On-Reset (POR) 1.8% Accuracy over all operating conditions function for each output. The POR delay for VO2 can be Excellent load regulation: <0.1% voltage change across full externally programmed by connecting a timing capacitor to the range of load current CPOR pin. The POR delay for VO1 is internally fixed at Extremely low quiescent current: 47A (both LDOs active) approximately 2ms. A reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high- Wide input voltage capability: 2.3V to 6.5V PSRR applications. Low dropout voltage: typically 300mV at 300mA The quiescent current is typically only 47A with both LDOs Low output noise: typically 37V at 100A (1.5V) RMS enabled and active. Separate enable pins control each Stable with 1F to 10F ceramic capacitors individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.5A. Separate enable and POR pins for each LDO Soft-start and staged turn-on to limit input current surge The part operates down to 2.3V and up to 6.5V input. The during enable typical output voltage can be as low as 1.2V and as high as 3.3V for each regulator. Please refer to the Ordering Current limit and over-temperature protection Information on page 3 for standard options. Tiny 10 Lead 3mm x 3mm DFN package The ISL78302 is AEC-Q100 qualified at the automotive AEC-Q100 qualified temperature range of -40C to +105C. Pb-free (RoHS Compliant) Applications Radio receivers Camera modules GPS/navigation Infotainment systems ISL78302 10 1 VIN (2.3 TO 6.5V) VIN VO1 V OUT1 ON 9 2 EN1 VO2 V ENABLE1 OUT2 V OK ON OUT2 OFF 3 8 EN2 POR2 ENABLE2 RESET2 OFF 7 V TOO LOW 4 (200ms DELAY, OUT2 CBYP POR1 C3 = 0.01F) V OK 5 6 OUT1 CPOR GND RESET1 (2ms DELAY) V TOO LOW C1 C2 C3 C4 C5 OUT1 C1, C4, C5: 1F X5R CERAMIC CAPACITOR C2: 0.01F X7R CERAMIC CAPACITOR C3: 0.01F X7R CERAMIC CAPACITOR FIGURE 1. TYPICAL APPLICATION FN7696 Rev 6.00 Page 1 of 13 November 6, 2014ISL78302 Block Diagram VIN VO1 VO2 LDO VO1 ERROR AMPLIFIER ~1.0V VO2 VREF TRIM POR COMPARATOR IS1 QEN1 1V VOK1 VOK2 POR1 LDO-1 POR2 LDO-2 VO2 EN1 CONTROL POR2 LOGIC POR2 VOK2 EN2 DELAY CBYP VO1 BANDGAP AND TEMPERATURE UVLO SENSOR POR1 POR1 1.00V VOLTAGE VOK1 DELAY REFERENCE 0.94V GENERATOR 0.90V GND CPOR FN7696 Rev 6.00 Page 2 of 13 November 6, 2014 IS1 IS2 QEN1 QEN2 100k 100k