DATASHEET ISL80102, ISL80103 FN6660 Rev.9.02 High Performance 2A and 3A Linear Regulators Jun 11, 2020 The ISL80102 and ISL80103 are low voltage, high-current, Features single output LDOs specified for 2A and 3A output current, Stable with ceramic capacitors (Note 11) respectively. These LDOs operate from the input voltages of 2.2V to 6V and are capable of providing the output voltages of 2A and 3A output current ratings 0.8V to 5.5V. 2.2V to 6V input voltage range An external capacitor on the soft-start pin provides adjustment 1.8% V accuracy assured over line, load, and T = -40C OUT J for applications that demand inrush current less than the to +125C current limit. The ENABLE feature allows the part to be placed Very low 120mV dropout voltage at 3A (ISL80103) into a low quiescent current shutdown mode. A submicron BiCMOS process is used for this product family to deliver Very fast transient response best-in-class analog performance and overall value. Excellent 62dB PSRR These CMOS (LDOs) consume significantly lower quiescent 49V output noise RMS current as a function of load over bipolar LDOs, so they are Power-good output more efficient and allow packages with smaller footprints. The quiescent current has been modestly compromised to enable Adjustable inrush current limiting a leading class fast load transient response, and hence a lower Short-circuit and over-temperature protection total AC regulation band for an LDO in this category. Available in a 10 Ld DFN Related Literature Applications For a full list of related documents, visit our website Servers ISL80102, ISL80103 product pages Telecommunications and networking Medical equipment Instrumentation systems Routers and switchers ISL80102, ISL80103 1.8V 2.5V 10% 1 9 V V V OUT OUT IN V IN C 2 OUT C 10 IN V V OUT IN 10F 10F R PG 100k R 1 10k 4 PGOOD PG 7 ENABLE EN OPEN DRAIN COMPATIBLE **C PB R 3 6 SS 2.61k 47pF 3 ADJ *C SS GND R 5 4 1.0k *CSS is optional (see Note 12 on page 5). **C is optional (see Functional Description on page 12 for more information). PB FIGURE 1. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION FN6660 Rev.9.02 Page 1 of 16 Jun 11, 2020ISL80102, ISL80103 Pin Descriptions TABLE 1. COMPONENTS VALUE SELECTION PIN PIN V R R C C OUT TOP BOTTOM PB OUT NUMBER NAME DESCRIPTION (V) (k ) ( ) (pF) (F) 1, 2 V Output voltage pin 5.0 2.61 287 47 10 OUT 3 ADJ ADJ pin for externally set V . 3.3 2.61 464 47 10 OUT 4PG V in regulation signal. Logic low defines when 2.5 2.61 649 47 10 OUT V is not in regulation. Must be grounded if not OUT 1.8 (Note 1) 2.61 1.0k 47 10 used. 1.8 (Note 1) 2.61 1.0k 82 22 5GND GND pin 1.5 2.61 1.3k 82 22 6 SS External cap adjusts inrush current. Leave this pin open if not used. 1.2 2.61 1.87k 150 47 7ENABLE V independent chip enable. TTL and CMOS IN 1.0 2.61 2.61k 150 47 compatible. 0.8 2.61 4.32k 150 47 8 DNC Do not connect this pin to ground or supply. Leave NOTE: floating. 1. Either option can be used depending on cost/performance 9, 10 V Input supply pin IN requirements EPAD EPAD must be connected to a copper plane with as many vias as possible for proper electrical and Pin Configuration optimal thermal performance. 10 LD 3x3 DFN TOP VIEW Block Diagram V V 1 10 OUT IN V V 2 9 OUT IN ADJ 3 EPAD 8 DNC PG 4 7 ENABLE GND 5 6 SS V IN R 5 IL/10000 M4 10A 10A M5 M3 M1 POWER PMOS IL V OUT + R 8 M6 - R 1 R R 9 EN 7 - 500mV + EN R 4 EN + ADJ ENEN - PG ENABLE M7 - ++ 500mV M2 -- + SS V TO I + *R 485mV 3 M8 EN - GND *R is open for ADJ versions. 3 FIGURE 2. BLOCK DIAGRAM FN6660 Rev.9.02 Page 2 of 16 Jun 11, 2020