DATASHEET ISL80111, ISL80112, ISL80113 FN7841 Rev 3.00 Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs September 30, 2016 The ISL80111, ISL80112, and ISL80113 are ultra low dropout Features LDOs providing the optimum balance between performance, size Ultra low dropout: 75mV at 3A, (typical) and power consumption in size constrained designs for data communication, computing, storage and medical applications. Excellent V PSRR: 70dB at 1kHz (typical) IN These LDOs are specified for 1A, 2A and 3A of output current and 1.6% guaranteed V accuracy for -40C < T < +125C OUT J are optimized for low voltage conversions. Operating with a V of IN Very fast load transient response 1V to 3.6V and with a legacy 2.9V to 5.5V on the BIAS, the V is OUT adjustable from 0.8V to 3.3V. With a V PSRR greater than 40dB IN Extensive protection and reporting features at 100kHz makes these LDOs an ideal choice in noise sensitive V range: 1V to 3.6V, V range: 0.8V to 3.3V IN OUT applications. The guaranteed 1.6% V accuracy overall OUT conditions lend these parts to supplying an accurate voltage to Small 10 Ld 3x3 DFN package the latest low voltage digital ICs. Applications An enable input allows the part to be placed into a low quiescent Noise-sensitive instrumentation and medical systems current shutdown mode. A submicron CMOS process is utilized for this product family to deliver best-in-class analog performance Data acquisition and data communication systems and overall value for applications in need of input voltage Storage, telecommunications and server equipment conversions typically below 2.5V. It also has the superior load Low voltage DSP, FPGA and ASIC core power supplies transient regulation unique to a NMOS power stage. These LDOs consume significantly lower quiescent current as a function of Post-regulation of switched mode power supplies load compared to bipolar LDOs. Related Literature UG009, ISL8011xEVAL1Z Evaluation Board User Guide 100 ISL80111, ISL80112, ISL80113 90 3A 1.0V 1.2V 5% 80 9 1 VOUT VOUT VIN VIN C C 2 70 IN 10 OUT VOUT VIN 10F 10F 2A 60 3.3V 10% 4 50 VBIAS VBIAS 6 C PGOOD PG BIAS 40 1F 1A R 3 30 1.0k 3 7 ADJ 20 ENABLE EN GND R 4 10 1.0k OPEN-DRAIN COMPATIBLE 5 0 -40 25 85 125 TEMPERATURE ( C) FIGURE 1. TYPICAL APPLICATION SCHEMATIC FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND I OUT 100 1.015 1.010 80 I = 1A OUT 1.005 60 I = 0A OUT I = 2A 1.000 OUT 40 I = 3A OUT 0.995 BIAS = 5V V = 3.3V 20 IN 0.990 V = 2.5V OUT C = 10F OUT 0 0.985 100 1k 10k 100k 1M -40 0 25 85 125 FREQUENCY (Hz) TEMPERATURE (C) FIGURE 4. V vs TEMPERATURE FIGURE 3. V PSRR vs LOAD CURRENT (ISL80113) ADJ IN FN7841 Rev 3.00 Page 1 of 16 September 30, 2016 PSRR (dB) V +25C NORMALIZED ADJ DROPOUT VOLTAGE, BIAS = 5V (mV)ISL80111, ISL80112, ISL80113 Block Diagram VIN VBIAS CURRENT LIMIT BIAS UVLO VIN M3 M1 POWER NMOS VIN DRIVER UVLO IL EN IL/10,000 VOUT R7 THERMAL SHUTDOWN EN ENEN ADJ - EN + PG ENABLE M7 - ++ M 500mV 2 -- + + 425mV - GND FIGURE 5. BLOCK DIAGRAM Pin Configuration Pin Descriptions ISL80111, ISL80112, ISL80113 (10 LD 3X3 DFN) PIN TOP VIEW NUMBER PIN NAME DESCRIPTION 1, 2 VOUT Output voltage pin. Range 0.8V to 3.3V VOUT 1 10 VIN 3 ADJ ADJ pin for externally setting V . OUT VOUT 2 9 VIN 4 VBIAS Bias voltage pin for internal control circuits. ADJ 3 8 NC EPAD (GND) Range 2.9V to 5.5V VBIAS ENABLE 4 7 5GND Ground pin GND 5 6 PG 6PG V in regulation signal. Logic low defines OUT when V is not in regulation. Range 0V to OUT BIAS 7ENABLE V independent chip enable. TTL and CMOS IN compatible. Range 0V to V V must BIAS. EN always be less than or equal to the voltage applied to VBIAS. When this pin is not used, it must be tied to VBIAS. 8 NC No Connect 9, 10 VIN Input supply pins. Range 1.0V to 3.6V EPAD EPAD at ground potential. It is recommended to solder the EPAD to the ground plane. FN7841 Rev 3.00 Page 2 of 16 September 30, 2016