DATASHEET ISL8120 FN6641 Rev.3.00 Dual/n-Phase Buck PWM Controller with Integrated Drivers July 20, 2016 The ISL8120 integrates two voltage-mode PWM leading-edge Features modulation control, with input feed-forward synchronous buck Wide V range operation: 3V to 22V PWM controllers, to control a dual independent voltage IN regulator or a 2-phase single output regulator. It also -V operation from 3V to 5.60V CC integrates current sharing control for the power module to Excellent output voltage regulation: 0.6V 0.6%/0.9% operate in parallel, which offers high system flexibility. internal reference over commercial/industrial temperature The ISL8120 integrates an internal linear regulator, which Frequency synchronization generates VCC from input rail for applications with only one Programmable phase shift for 1-, 2-, 3-, 4-, 6-, up to single supply rail. The internal oscillator is adjustable from 12-phase applications 150kHz to 1.5MHz, and is able to synchronize to an external clock signal for frequency synchronization and phase paralleling Fault hand shake capability for high system reliability applications. Its PLL circuit can output a phase-shift Digital soft-start with precharged output start-up capability programmable clock signal for the system to be expanded to 3-, Dual independent channel enable inputs with precision 4-, 6-, 12- phases with desired interleaving phase shift. voltage monitor and voltage feed-forward capability The ISL8120s Fault Hand Shake feature protects any channel - Programmable input voltage POR and its hysteresis with a from overloading/stressing due to system faults or phase resistor divider at EN input failure. The undervoltage fault protection features are also designed to prevent a negative transient on the output voltage Extensive circuit protection functions: output overvoltage, during falling down. This eliminates the Schottky diode that is undervoltage, overcurrent protection, over temperature and used in some systems for protecting the load device from pre-power-on reset overvoltage protection option reversed output voltage damage. Applications Related Literature Power supply for datacom/telecom and POL Technical Brief TB389 PCB Land Pattern Design and Surface Paralleling power module Mount Guidelines for QFN (MLFP) Packages Wide and narrow input voltage range buck regulators AN1528, ISL8120EVAL3Z Evaluation Board Setup DDR I and II applications Procedure High current density power supplies AN1607, ISL8120EVAL4Z Evaluation Board Setup Procedure Multiple outputs VRM and VRD PVCC CHANNELS 1 AND 2 GATE DRIVE 3 BOOTn UGATEn PWMn 10k SHOOT- GATE THROUGH PHASEn FAULT LOGIC CONTROL PROTECTION LOGIC 10k LGATEn FIGURE 1. INTEGRATED DRIVER BLOCK DIAGRAM FN6641 Rev.3.00 Page 1 of 39 July 20, 2016ISL8120 Table of Contents Pin Configuration 3 Functional Pin Descriptions . 3 Ordering Information 5 Controller Block Diagram . 6 Typical Application Circuits . 7 2-Phase Operation with DCR Sensing .7 2-Phase Operation with r Sensing 8 DS(ON) Dual Regulators with DCR Sensing and Remote Sense 9 Double Data Rate I or II 10 3-Phase Regulator with Precision Resistor Sensing . 11 4-Phase Operation with DCR Sensing . 12 Multiple Power Modules in Parallel with Current Sharing Control 13 3-Phase Regulator with Resistor Sensing and 1 Phase Regulator . 14 6-Phase Operation with DCR Sensing . 15 Absolute Maximum Ratings 16 Thermal Information 16 Recommended Operating Conditions . 16 Electrical Specifications 16 Typical Performance Curves . 19 Modes of Operation . 21 Functional Description 23 Initialization 24 Voltage Feed-Forward 24 Soft-Start . 25 Power-Good 25 Overvoltage and Undervoltage Protection . 25 PRE-POR Overvoltage Protection (PRE-POR-OVP) . 26 Over-Temperature Protection (OTP) 26 Inductor Current Sensing . 26 Resistive Sensing 27 Overcurrent Protection . 28 Current Sharing Loop 29 Internal Series Linear and Power Dissipation 32 Oscillator . 33 Frequency Synchronization and Phase Lock Loop 33 Differential Amplifier for Remote Sense 33 Internal Reference and System Accuracy 34 DDR and Dual Mode Operation 35 Layout Considerations 36 Revision History 38 About Intersil 38 Package Outline Drawing 39 FN6641 Rev.3.00 Page 2 of 39 July 20, 2016