USERS MANUAL ISL8120EVAL4Z AN1607 Rev.2.00 Evaluation Board Setup Procedure Jul 1, 2016 Description Circuits Description The ISL8120 integrates two voltage-mode synchronous buck J1 and J2 are the input power terminals. PWM controllers. It can be used either for dual independent J3 and J4 are output lugs for load connections. outputs or a 2-phase single-output regulator. The input electrolytic capacitors are used to handle the input The ISL8120EVAL4Z evaluation board is used for performance current ripples. demo of 2/n-phase single-output applications. This application note introduces the setup procedure and performance of the Two upper and two lower Renesas speed series LFPAK ISL8120EVAL4Z evaluation board. MOSFETs are used for each phase. The ISL8120EVAL3Z evaluation board is for performance 320nH PULSE surface mount inductors are used for each demo of dual independent outputs and DDR applications. phase. Under the 500kHz setup, the inductor current Refer to application note AN1528 ISL8120EVAL3Z Evaluation peak-to-peak ripple is 7.5A at 12V input and 1.2V output. Board Setup Procedure for details of the ISL8120EVAL3Z Four SANYO POSCAP 2R5TPF470M7L (7m ) are used as board. output E-caps. TP2 and TP3 are remote sense posts. These pins can be used References to monitor and evaluate the system voltage regulations. If the ISL8120 datasheet user wants to use these test posts for remote sense, the R 29 and R need to be changed to higher values, such as 10 . 31 Ordering Information Also, the related voltage sense divider needs to be increased to a higher resistance, such as 1k. PART NUMBER DESCRIPTION TP1 is a test socket to hold the scope probe to check the ISL8120EVAL4Z IISL8120EVAL4Z evaluation board output waveforms. JP9 is used to disable the part. Recommended Equipment JP6 is for connection of inputs of clock signal for the part to be 0V to 22V power supply with at least 20A source current synchronized with. capability, battery, or notebook AC adapter. JP5 is used for connection of ISHARE signals of multiple Two electronic loads capable of sinking current up to 30A. boards in parallel operation applications. Digital multimeters (DMMs). JP3, JP4, R and R are used to set up the phase shift 15 17 between the 2 phases of the IC. 100MHz quad-trace oscilloscope. R is used to isolate the noise at PVCC caused by driving. In 27 Quick Start 3.3V applications, it is recommended to short R to 0 in order 27 to prevent VCC from dropping below POR under low input 1. Ensure that the circuit is correctly connected to the supply voltage. and loads prior to applying any power. 2. Adjust the input supply to be 12V. Turn on the input power Evaluating the Other Output supply. Voltage 3. Verify the output voltage is 1.2V. If PGOOD is set high, the LED2 will be green. If PGOOD is set low, the LED2 will be The ISL8120EVAL4Z kit output is preset to 1.2V/50A. V OUT1 red. TP4 is the test post to monitor PGOOD. can also be adjusted between 0.6V to 3V by changing the value of R and R for V , as given by Equation 1. The same rule 26 6 OUT applies for V . OUT2 R 6 R = ------------------------------------------------- where V = 0.6V (EQ. 1) REF 26 V V 1 OUT REF AN1607 Rev.2.00 Page 1 of 12 Jul 1, 2016Evaluation Board Setup Procedure ISL8120EVAL4Z FIGURE 1. ISL8120EVAL4Z EVALUATION BOARD Programming the Input Voltage Parallel Operation for Current UVLO and its Hysteresis Sharing Application By programming the voltage divider at the EN/FF pin connected The ISL8120 regulator outputs can be paralleled with current to the input rail, the input UVLO and its hysteresis can be sharing control capability. The configuration for parallel programmed. The ISL8120EVAL4Z has R 4.32k and R operation is shown in Typical Application VIII in the datasheet. 20 21 1.62k the IC will be disabled when input voltage drops below For this evaluation board, follow these steps to set up the parallel 2.94V and will restart until V recovers to be above 3.2V. operation of 2 boards: IN For 12V applications, it is suggested to have R 24.9k and R 1. Change R to 100 for both boards. 20 21 5 2.43k, of which the IC is disabled when the input voltage drops 2. Use 2 wires (ISHARE, GND) connecting the ISHARE signals of below 9V and will restart until V recovers to be above 10.5V. IN the 2 boards through JP5. Refer to the ISL8120 datasheet to program the UVLO falling 3. Use 2 wires (EN/FF, GND) connecting the EN/FF signals of the threshold and hysteresis. The equations are restated here in 2 boards through JP9. Equations 2 and 3, where R and R are the upper and UP DOWN 4. Use 2 wires connecting from JP10 (CLKOUT, GND) of one lower resistors of the voltage divider at EN/FF pin, V is the HYS board to JP6 (FSYNC, GND) of another board. desired UVLO hysteresis and V is the desired UVLO falling FTH 5. Connecting the power supply to the inputs of the 2 boards. threshold. 6. Connecting the output of the 2 boards together and apply the V HYS loads. R --------------- where I = 2x30A (EQ. 2) = HYS UP I HYS Figure 2 shows the setup picture of 2 boards in parallel operation. R V UP ENREF (EQ. 3) R = -------------------------------------------- where V = 0.8V ENREF DOWN V V FTH ENREF Note the ISL8120 EN/FF pin is a triple function pin and the voltages applied to the EN/FF pins are also fed to adjust the amplitude of each channels individual sawtooth. AN1607 Rev.2.00 Page 2 of 12 Jul 1, 2016