Wide V Dual Standard Buck Regulator With 3A/3A IN Continuous Output Current ISL85033 Features The ISL85033 is a dual standard buck regulator capable of 3A Wide Input Voltage Range from 4.5V to 28V per channel continuous output current. With an input range of Adjustable Output Voltage with Continuous Output Current 4.5V to 28V, it provides a high frequency power solution for a up to 3A variety of point of load applications. Current Mode Control The PWM controller in the ISL85033 drives an internal Adjustable Switching Frequency from 300kHz to 2MHz switching N-Channel power MOSFET and requires an external Independent Power-Good Detection Schottky diode to generate the output voltage. The integrated power switch is optimized for excellent thermal performance Selectable In-Phase or Out-of-Phase PWM Operation up to 3A of output current. The PWM regulator switches at a Independent, Sequential, Ratiometric or Absolute Tracking default frequency of 500kHz and it can be user programmed Between Outputs or synchronized from 300kHz to 2MHz. The ISL85033 utilizes Internal 2ms Soft-start Time peak current mode control to provide flexibility in component selection and minimize solution size. The protection features Overcurrent/Short Circuit Protection, Thermal Overload include overcurrent, UVLO and thermal overload protection. Protection, UVLO The ISL85033 is available in a small 4mmx4mm Thin Quad Boot Undervoltage Detection Flat Pb-free (TQFN) package. Pb-Free (RoHS Compliant) Related Literature Applications See AN1574 ISL85033DUALEVAL1Z Wide VIN Dual General Purpose Point of Load DC/DC Power Conversion Standard Buck Regulator With 3A/3A Output Current Set-top Boxes FPGA Power and STB Power DVD and HDD Drives LCD Panels, TV Power Cable Modems 100 90 12V 1MHz OUT 80 70 60 50 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) FIGURE 1. EFFICIENCY vs LOAD, V = 28V, T = +25C IN A February 23, 2012 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2010, 2011, 2012. All Rights Reserved FN6676.6 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. EFFICIENCY (%) ISL85033 Pin Configuration ISL85033 (28 LD TQFN) TOP VIEW 28 27 26 25 24 23 22 COMP1 21 COMP2 1 FB1 20 FB2 2 SS1 19 SS2 3 PGND1 18 PGND2 4 PD BOOT1 17 BOOT2 5 PHASE1 16 PHASE2 6 15 PHASE1 PHASE2 7 89 10 11 12 13 14 Pin Descriptions PIN NUMBER SYMBOL PIN DESCRIPTION 1, 21 COMP1, COMP2 COMP1/COMP2 is the output of the error amplifier. 2, 20 FB1, FB2 Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In addition, the PWM regulators power-good and undervoltage protection circuits use FB1/2 to monitor the regulator output voltage. 3, 19 SS1, SS2 Soft-Start pins for each controller. The SS1/2 pins control the soft-start and sequence of their respective outputs. A single capacitor from the SS pin to ground determines the output ramp rate. See the Output Tracking and Sequencing on page 16 for soft-start and output tracking/sequencing details. If SS pins are tied to VCC, an internal soft-start of 2ms will be used. Maximum C value is 50nF. SS 4, 18 PGND1, PGND2 Power ground connections. Connect directly to the system GND plane. 5, 17 BOOT1, BOOT2 Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn on the internal N-Channel MOSFET. Connect an external capacitor from this pin to PHASE. 6, 7, 15, 16 PHASE1, PHASE2 Switch node output. It connects the source of the internal power MOSFET with the external output inductor and with the cathode of the external diode. 8, 9, 13, 14 VIN1, VIN2 The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides bias for the IC. Place a minimum of 10F ceramic capacitance from each VIN to GND and close to the IC for decoupling. 10, 12 EN1, EN2 PWM controllers enable inputs. The PWM controllers are held off when the pin is pulled to ground. When the voltage on this pin rises above 2V, the PWM controller is enabled. If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be: EN T off ()s = 10 sC 2.2nF SS where C is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external SS signals. 11 VCC Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7F ceramic capacitor. This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA). FN6676.6 2 February 23, 2012 PGOOD1 VIN1 FS VIN1 NC EN1 SGND VCC SYNCIN EN2 SYNCOUT VIN2 PGOOD2 VIN2