Datasheet ISL89163, ISL89164, ISL89165 High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs The ISL89163, ISL89164, and ISL89165 are Features high-speed, 6A, dual channel MOSFET drivers with Dual output, 6A peak currents, can be paralleled enable inputs. Dual AND-ed input logic, (input and enable) Precision thresholds on all logic inputs allow the use Typical ON-resistance <1 of external RC circuits to generate accurate and stable time delays on both the main channel inputs, Specified Miller plateau drive currents INA and INB, and the enable inputs, ENA and ENB. Very low thermal impedance ( = 3C/W) JC The precision delays capable of these precise logic thresholds make these parts valuable for dead time Hysteretic Input logic levels for 3.3V CMOS, 5V control and synchronous rectifiers. Note, the enable CMOS, TTL, and Logic levels proportional to V DD and input logic inputs can be interchanged for Precision threshold inputs for time delays with alternate logic implementations. external RC components Three input logic thresholds are available: 20ns rise and fall time driving a 10nF load. 3.3V (CMOS) Applications 5.0V (CMOS or TTL compatible) Synchronous Rectifier (SR) driver CMOS thresholds that are proportional to V DD Switch mode power supplies At high switching frequencies, these MOSFET drivers Motor drives, Class D amplifiers, UPS, inverters use a minimal amount of internal bias currents. Separate, non-overlapping drive circuits are used to Pulse transformer driver drive each CMOS output FET to prevent Clock/line driver shoot-through currents in the output stage. Related Literature The start-up sequence is designed to prevent unexpected glitches when V is being turned on or DD For a full list of related documents, visit our website: turned off. When V < ~1V, an internal 10k resistor DD ISL89163, ISL89164, ISL89165 device pages between the output and ground helps to keep the output voltage low. When ~1V < V < UV, both DD outputs are driven low with significantly low resistance as the logic inputs are ignored, which ensures that the driven FETs are off. When V > UVLO, and after a DD short delay, the outputs begin to respond to the logic inputs. 3.0 Positive Threshold Limits 2.5 V DD 2.0 ENB ENA 1 8 1.5 INA OUTA Negative Threshold Limits 2 7 EPAD GND 3 6 1.0 INB OUTB 4 5 0.5 4.7F 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (C) Figure 1. Typical Application Figure 2. Temperature Stable Logic Thresholds FN7707 Rev.6.00 Page 1 of 22 Jul.9.19 Option B Thresholds (5.0V)ISL89163, ISL89164, ISL89165 Contents 1. Overview . 3 1.1 Block Diagram 3 1.2 Ordering Information . 3 1.3 Pin Configurations . 5 1.4 Pin Descriptions . 5 2. Specifications . 6 2.1 Absolute Maximum Ratings 6 2.2 Thermal Information 6 2.3 Recommended Operating Conditions 7 2.4 Electrical Specifications . 7 2.5 AC Electrical Specifications 8 2.6 Test Waveforms and Circuits . 9 3. Typical Performance Curves 11 4. Functional Description 13 5. Application Information 14 5.1 Precision Thresholds for Time Delays . 14 5.2 Paralleling Outputs to Double the Peak Drive Currents 14 5.3 Power Dissipation of the Driver 15 5.4 Typical Application Circuits . 15 6. General PCB Layout Guidelines . 17 7. General EPAD Heatsinking Considerations . 18 8. Revision History 19 9. Package Outline Drawings . 20 FN7707 Rev.6.00 Page 2 of 22 Jul.9.19