High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs ISL89163, ISL89164, ISL89165 Features The ISL89163, ISL89164, and ISL89165 are high-speed, 6A, Dual output, 6A peak currents, can be paralleled dual channel MOSFET drivers with enable inputs. These parts are Dual AND-ed input logic, (INput and ENable) very similar to the ISL89160, ISL89161, ISL89162 drivers but Typical ON-resistance <1 with an added enable input for each channel occupying NC pins 1 and 8 of the ISL89160, ISL89161, ISL89162. Specified Miller plateau drive currents Very low thermal impedance ( = 3C/W) Precision thresholds on all logic inputs allow the use of external JC RC circuits to generate accurate and stable time delays on both Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, TTL and the main channel inputs, INA and INB, and the enable inputs, Logic levels proportional to V DD ENA and ENB. The precision delays capable of these precise logic Precision threshold inputs for time delays with external RC thresholds makes these parts very useful for dead time control components and synchronous rectifiers. Note that the ENable and INput logic inputs can be interchanged for alternate logic implementations. 20ns rise and fall time driving a 10nF load. Three input logic thresholds are available: 3.3V (CMOS), 5.0V Applications (CMOS or TTL compatible), and CMOS thresholds that are Synchronous Rectifier (SR) Driver proportional to VDD. Switch mode power supplies At high switching frequencies, these MOSFET drivers use very little internal bias currents. Separate, non-overlapping drive Motor Drives, Class D amplifiers, UPS, Inverters circuits are used to drive each CMOS output FET to prevent Pulse Transformer driver shoot-thru currents in the output stage. Clock/Line driver The start-up sequence is design to prevent unexpected glitches when V is being turned on or turned off. When V < ~1V, an DD DD Related Literature internal 10k resistor between the output and ground helps to AN1603 ISL6752/54EVAL1Z ZVS DC/DC Power Supply with keep the output voltage low. When ~1V < V < UV, both outputs DD Synchronous Rectifiers User Guide are driven low with very low resistance and the logic inputs are ignored. This insures that the driven FETs are off. When V > UVLO, and after a short delay, the outputs now respond to DD the logic inputs. 3.0 POSITIVE THRESHOLD LIMITS V DD 2.5 ENB ENA 8 1 2.0 INA OUTA 2 7 EPAD GND 1.5 6 3 NEGATIVE THRESHOLD LIMITS INB OUTB 4 5 1.0 4.7F 0.5 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) FIGURE 1. TYPICAL APPLICATION FIGURE 2. TEMP STABLE LOGIC THRESHOLDS March 7, 2012 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2010-2012. All Rights Reserved FN7707.3 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. OPTION B THRESHOLDS (5.0V)ISL89163, ISL89164, ISL89165 Block Diagram VDD FOR OPTIONS A AND B, THE UV SEPARATE FET DRIVES, WITH NON-OVERLAPPING FOR CLARITY, ONLY ONE COMPARATOR HOLDS OFF THE OUTPUTS, PREVENT SHOOT-THRU CURRENTS IN CHANNEL IS SHOWN OUTPUTS UNTIL VDD ~> 3.3VDC. THE OUTPUT CMOS FETS RESULTING WITH VERY FOR OPTION C, THE UV RELEASE LOW HIGH FREQUENCY OPERATING CURRENTS. IS ~> 6.5V ENx ISL89163 ENX AND INX INPUTS ARE IDENTICAL AND MAY BE INTERCHANGED FOR ALTERNATE LOGIC OUTx INx 10k ISL89164, ISL89165 GND EPAD FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE, THE EPAD MUST BE CONNECTED TO THE PCB GROUND PLANE. Pin Configurations Pin Descriptions DESCRIPTION ISL89163FR, ISL89163FB ISL89164FR, ISL89164FB PIN (See Truth Table for (8 LD TDFN, EPSOIC) (8 LD TDFN, EPSOIC) NUMBER SYMBOL Logic Polarities) TOP VIEW TOP VIEW 1 ENA Channel A enable, 0V to VDD ENA 1 8ENB ENA 1 8ENB 2 INA, /INA Channel A input, 0V to VDD INA 2 7OUTA /INA 2 7OUTA 3 GND Power Ground, 0V GND 3 6VDD GND 3 6VDD 4 INB, /INB Channel B enable, 0V to VDD INB 4 5OUTB /INB 4 5OUTB 5OUTB Channel B output 6 VDD Power input, 4.5V to 16V ISL89165FR, ISL89165FB 7 OUTA Channel A output, 0V to VDD (8 LD TDFN, EPSOIC) TOP VIEW 8 ENB Channel B enable, 0V to VDD EPAD Power Ground, 0V ENA 1 8ENB /INA 2 7OUTA ENx ENx GND 3 6VDD OUTx OUTx INx /INx INB 4 5OUTB NON-INVERTING INVERTING ENx* INx* OUTx* UV UV ENx* /INx* OUTx* 0 x x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 *SUBSTITUTE A OR B FOR x FN7707.3 2 March 7, 2012