DATASHEET ISL9000A FN6391 Rev 3.00 Dual LDO with Low Noise, Very High PSRR and Low IQ October 15, 2015 ISL9000A is a high performance dual LDO capable of sourcing Features 300mA current from each output. It has a low standby current Integrates two 300mA high performance LDOs and very high PSRR and is stable with output capacitance of 1F to 10F with ESR of up to 200m. Excellent transient response to large current steps The device integrates an individual Power-On-Reset (POR) 1.8% accuracy over all operating conditions function for each output. The POR delay for VO2 can be Excellent load regulation: < 0.1% voltage change across full externally programmed by connecting a timing capacitor to the range of load current CPOR pin. The POR delay for VO1 is internally fixed at Low output noise: typically 30V 100A (1.5V) RMS approximately 2ms. A reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high- Very high PSRR: 90dB 1kHz PSRR applications. Extremely low quiescent current: 42A (both LDOs active) The quiescent current is typically only 42A with both LDOs Wide input voltage capability: 2.3V to 6.5V enabled and active. Separate enable pins control each Low dropout voltage: typically 200mV 300mA individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1A. Stable with 1F to 10F ceramic capacitors Separate enable and POR pins for each LDO Several combinations of voltage outputs are standard. Output voltage options for each LDO range from 1.5V to 3.3V. Other Soft-start and staged turn-on to limit input current surge output voltage options may be available upon request. during enable Current limit and overheat protection Tiny 10 Ld 3mmx3mm DFN package -40C to +85C operating temperature range Pb-free (RoHS compliant) Applications PDAs, Cell Phones and Smart Phones Portable Instruments, MP3 Players Handheld Devices including Medical Handheld ISL9000A 1 10 VIN (2.3 TO 6.5V) VO1 VIN VO1 ON 2 9 ENABLE1 EN1 VO2 VO2 VO2 OK ON OFF 3 8 EN2 POR2 ENABLE2 RESET2 OFF 7 4 VO2 TOO LOW (200ms DELAY, CBYP POR1 C3 = 0.01F) V OK 6 OUT1 5 CPOR GND RESET1 (2ms DELAY) VO1 TOO LOW C1 C2 C3 C4 C5 C1, C4, C5: 1F X5R CERAMIC CAPACITOR C2: 0.1F X7R CERAMIC CAPACITOR C3: 0.01F X7R CERAMIC CAPACITOR FIGURE 1. TYPICAL APPLICATION FN6391 Rev 3.00 Page 1 of 14 October 15, 2015ISL9000A Block Diagram VIN VO1 VO2 LDO VO1 ERROR AMPLIFIER ~1.0V VO2 VREF TRIM POR COMPARATOR IS1 QEN1 1V VOK1 VOK2 POR1 LDO-1 POR2 LDO-2 VO1 EN1 CONTROL POR2 LOGIC POR2 VOK2 EN2 DELAY CBYP VO2 BANDGAP AND TEMPERATURE UVLO SENSOR POR1 POR1 1.00V VOLTAGE VOK1 DELAY REFERENCE 0.94V GENERATOR 0.90V GND CPOR FN6391 Rev 3.00 Page 2 of 14 October 15, 2015 IS1 IS2 QEN1 QEN2 100k 100k