D3 CMS06 19 3 EXTM NC 15 24 TDOUT VOUT 14 26 TDIN VSW 18 2 TXT VSWSNS 13 7 SVTOP DRAIN 12 8 ADDR1 PGND 11 ADDR0 DATASHEET ISL9492 FN6547 2 Rev 1.00 Single Output LNB Supply and Control Voltage Regulator with I C Interface for March 17, 2011 Satellite Set-Top Box Designs The ISL9492 is a highly integrated voltage regulator and Features interface IC specifically designed for supplying power and Single-Chip Power Solution control signals from advanced satellite set-top box (STB) - Operation for 1-Tuner/1-Dish Applications modules to the low noise blocks (LNB) of a single antenna port. 2 It also supports DiSEqC tone generation and modulation with - Integrated DC/DC Converter and I C Interface diagnostic status read-back. Controlling the ISL9492 is simple Integrated Boost MOSFET 2 via the I C bus by writing 8 bit words onto the System Switch-Mode Power Converter for Lowest Dissipation Registers (SR). - 490kHz Boost Switching Frequency The device design makes the total LNB supply design simple, - Boost PWMs with > 92% Efficiency efficient and compact with low external component count by - Selectable 13.5V or 18.5V Outputs integrating Boost power MOSFET, current-mode boost PWM 2 -I C and Pin Controllable Output and a low-noise linear regulator. The current-mode boost converters provide the linear regulator with input voltage that 31V Output Back-Bias Capability is set to the final output voltages, plus typically 0.9V to insure Built-in Tone Oscillator Factory minimum power dissipation across each linear regulator. - Facilitates DiSEqC (EUTELSAT) Encoding The LNB output voltage can be controlled in two ways by full -Trimmed to 22kHz 2 control from I C using the VTOP and VBOT bits or by setting the - External Modulation Input 2 I C to the lower range and switching to higher range with the select VTOP pin. DiSEqC 2.0 Support and Diagnostics Internal Overvoltage, Undervoltage, Overcurrent Protection, The External modulation input EXTM accepts a modulated 2 Over-Temperature Flags Accessible through the I C Interface DISEqC command and transfers it symmetrically to the output. and Fault Signal Status Pin The EXTM pin can be used to modulate the continuous internal tone. The fault signal serves as an interrupt for the processor Short-Circuit Protection when any condition turns OFF the LNB controller (over-temperature, overcurrent, disable). The states of these flags Applications 2 to the faults can be thoroughly examined through the I C LNB Power Supply and Control for Satellite Set-Top Box registers. TXT TDOUT EXTM FLT R1 27 21 CPVOUT FLT 3.3V C5 100k C1 28 CPSWOUT 0.047F 17 SCL SCL 2.2nF 1 CPSWIN 16 SDA SDA 6 VCC C2 1F ISL9492 C6 20 10 LDO SGND DBYP 0.1F C4 1F 25 22 LDO SGND TCAP C8 RL 5 4 0.22F ABYP NC 100 C3 1F 9 23 PGND DGATE FERRITE Q1 BEAD NDS356AP C9 LNB POWER 0.22F Cp C10 See pg 14 L3 0.1F Rp L1 L2 220H VIN D1 100 R2 10H 1H CMS06 15 C7 C10 C11 100F 100F 10F D4 CMS06 FIGURE 1. TYPICAL APPLICATION FN6547 Rev 1.00 Page 1 of 21 March 17, 2011 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc D2 TVSISL9492 Ordering Information PART NUMBER PART TEMP. PACKAGE PKG. (Notes 1, 2, 3) MARKING RANGE (C) (Pb-free) DWG. ISL9492ERZ 94 92ERZ -20 to +85 28 Ld 4x4 TQFN L28.4x4A ISL9492QFNEVAL1 Evaluation Board 1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9492. For more information on MSL please see techbrief TB363. Pin Configuration ISL9492 (28 LD TQFN) TOP VIEW 28 27 26 25 24 23 22 CPSWIN 1 FLT 21 2 VSWSNS 20 LDO SGND NC 3 19 EXTM NC 4 TXT 18 ABYP 5 17 SCL VCC 6 16 SDA DRAIN 7 15 TDOUT 8 910 11 12 13 14 Functional Pin Descriptions PIN SYMBOL FUNCTION 1 CPSWIN Charge pump connection 1 2 VSWSNS Boost regulator sense line. Connect to boost output capacitor. 3, 4 NC No connect pins 5 ABYP Analog 5V supply. Decouple with 1F ceramic capacitor and a ferrite bead (see ABYP on page 14 for more detail). 6 VCC Main power supply to the chip. 7 DRAIN This is the Drain of the Boost MOSFET. The Boost inductor will be connected to this pin. 8,9 PGND Power gound for the Internal Boost MOSFET. 10 DBYP Digital 5V supply. Decouple with 1F ceramic capacitor. 11, 12 ADDR0, ADDR1 Logic combination at the ADD0 and ADD1 can select four different chip select addresses. 13 SVTOP External control of output voltage selection. 14 TDIN Tone detector input. 15 TDOUT The envelope of the actually detected external tone signal. It is an open-drain output. FN6547 Rev 1.00 Page 2 of 21 March 17, 2011 PGND CPSWOUT PGND CPVOUT DBYP VSW LDO SGND ADDR0 VOUT ADDR1 DGATE SVTOP TDIN TCAP