DATASHEET ISLA212P13, ISLA212P20, ISLA212P25 FN7717 Rev.3.00 12-Bit, 250MSPS/200MSPS/130MSPS ADC Dec 13, 2019 The ISLA212P is a series of low power, high performance Features 12-bit analog-to-digital converters. Designed with the Renesas Single Supply 1.8V Operation proprietary FemtoCharge technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. Clock Duty Cycle Stabilizer The ISLA212P is part of a pin-compatible family of 12 to 16-bit 75fs Clock Jitter A/Ds with maximum sample rates ranging from 130MSPS to 700MHz Bandwidth 500MSPS. Programmable Built-in Test Patterns A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters Multi-ADC Support such as gain and offset. Digital output data is presented in - SPI Programmable Fine Gain and Offset Control selectable LVDS or CMOS formats, and can be configured as - Support for Multiple ADC Synchronization full-width, single data rate (SDR) or half-width, double data - Optimized Output Timing rate (DDR). The ISLA212P is available in a 72-contact QFN package with an exposed paddle. Operating from a 1.8V Nap and Sleep Modes supply, performance is specified over the full industrial - 200s Sleep Wake-up Time temperature range (-40C to +85C). Data Output Clock Key Specifications SDR/DDR LVDS-Compatible or LVCMOS Outputs SNR 250/200/130MSPS Selectable Clock Divider 70.5/71.0/71.5dBFS f = 30MHz IN Applications 68.7/68.9/68.8dBFS f = 363MHz IN Radar Array Processing SFDR 250/200/130MSPS 83/83/88dBc f = 30MHz Software Defined Radios IN 78/81/85dBc f = 363MHz IN Broadband Communications Total Power Consumption = 440mW 250MSPS High-Performance Data Acquisition Communications Test Equipment TABLE 1. PIN-COMPATIBLE FAMILY SPEED MODEL RESOLUTION (MSPS) ISLA216P25 16 250 ISLA216P20 16 200 ISLA216P13 16 130 CLKP CLKOUTP CLOCK ISLA214P50 14 500 MANAGEMENT CLKN CLKOUTN ISLA214P25 14 250 ISLA214P20 14 200 ISLA214P13 14 130 VINP 12-BIT D 11:0 P SHA 250 MSPS ISLA212P50 12 500 ADC VINN D 11:0 N ISLA212P25 12 250 DIGITAL ERROR CORRECTION + ISLA212P20 12 200 VCM SPI ISLA212P13 12 130 CONTROL FN7717 Rev.3.00 Page 1 of 38 Dec 13, 2019 AVSS AVDD NAPSLP RESETN CSB SCLK SDIO CLKDIV SDO CLKDIVRSTP CLKDIVRSTN RLVDS OVSS OVDDISLA212P13, ISLA212P20, ISLA212P25 Table of Contents Pin Configuration - LVDS MODE 4 Pin Descriptions - 72 Ld QFN, LVDS Mode . 5 Pin Configuration - CMOS MODE . 6 Pin Descriptions - 72 Ld QFN, CMOS Mode 7 Ordering Information 8 Absolute Maximum Ratings . 9 Thermal Information . 9 Electrical Specifications . 9 Digital Specifications . 11 Timing Diagrams . 12 Switching Specifications 14 Typical Performance Curves . 15 Theory of Operation . 18 Functional Description . 18 Power-On Calibration . 18 User Initiated Reset 19 Temperature Calibration . 20 Analog Input 21 Clock Input . 21 Jitter . 22 Voltage Reference . 22 Digital Outputs 22 Power Dissipation . 22 Nap/Sleep 22 Data Format 23 Clock Divider Synchronous Reset . 23 Serial Peripheral Interface 26 SPI Physical Interface 26 SPI Configuration 26 Device Information 27 Device Configuration/Control 27 Global Device Configuration/Control . 28 Digital Temperature Sensor . 29 SPI Memory Map . 31 Equivalent Circuits . 33 A/D Evaluation Platform . 34 Layout Considerations 34 Split Ground and Power Planes 34 Clock Input Considerations 34 Exposed Paddle . 34 Bypass and Filtering . 34 LVDS Outputs . 34 LVCMOS Outputs 34 Unused Inputs 34 Definitions 34 FN7717 Rev.3.00 Page 2 of 38 Dec 13, 2019