DATASHEET ISLA214P12 FN7982 Rev.4.0 High Performance 14-Bit, 125MSPS ADC Jul 6, 2021 The ISLA214P12 is a high performance 14-bit 125MSPS Features analog-to-digital converter offering very high dynamic range Multi-ADC Support and low power consumption. It is part of a pin-compatible family of 12- to 16-bit A/Ds with maximum sample rates - SPI programmable fine gain and offset control ranging from 125 to 500MSPS. This allows a design using -Multiple ADC synchronization the ISLA214P12 to accommodate any of the other - Optimized output timing pin-compatible A/Ds with minimal changes. Clock duty cycle stabilizer The ISLA214P12 is very flexible and can be designed into a Nap and Sleep modes wide variety of systems. A Serial Peripheral Interface (SPI) port allows access to its extensive configurability and provides Programmable built-in test patterns digital control over various analog parameters such as input SDR/DDR LVDS-compatible or LVCMOS outputs gain and offset. Digital output data is presented in selectable LVDS or CMOS formats and can be configured as full-width, Data output clock Single Data Rate (SDR) or half-width, Double Data Rate (DDR). Operating from a 1.8V supply, performance is specified across Key Specifications the full industrial temperature range (-40C to +85C). SNR at 125MSPS - 74.9dBFS f = 30MHz IN Applications - 70.9dBFS f = 363MHz IN Radar array processing SFDR at 125MSPS Software defined radio - 88dBc f = 30MHz IN Broadband communications - 84dBc f = 363MHz IN High performance data acquisition Total power consumption = 310mW Communications test equipment - - - TABLE 1. PIN-COMPATIBLE FAMILY SPEED MODEL RESOLUTION (MSPS) ISLA216P25 16 250 ISLA216P20 16 200 CLKP CLKOUTP CLOCK MANAGEMENT CLKN CLKOUTN ISLA216P13 16 130 ISLA214P50 14 500 ISLA214P25 14 250 VINP 14-BIT SHA 125 MSPS D 13:0 P ISLA214P20 14 200 VINN ADC D 13:0 N DIGITAL ISLA214P13 14 130 ERROR + CORRECTION VCM ISLA212P50 12 500 SPI CONTROL ISLA212P25 12 250 ISLA212P20 12 200 ISLA212P13 12 130 FN7982 Rev.4.0 Page 1 of 33 Jul 6, 2021 2012 Renesas Electronics AVSS AVDD NAPSLP RESETN CSB SCLK SDIO CLKDIV SDO CLKDIVRSTP CLKDIVRSTN RLVDS OVSS OVDDISLA214P12 Table of Contents Ordering Information 3 Pin Configuration - LVDS Mode 3 Pin Descriptions - 72 Ld QFN, LVDS Mode . 4 Pin Configuration - CMOS Mode . 5 Pin Descriptions - 72 Ld QFN, CMOS Mode 6 Absolute Maximum Ratings . 7 Thermal Information . 7 Electrical Specifications . 7 Digital Specifications 9 Timing Diagrams . 10 Switching Specifications 12 Typical Performance Curves . 13 Theory of Operation . 16 Functional Description . 16 Power-On Calibration . 16 User Initiated Reset 17 Temperature Calibration . 17 Analog Input 18 Clock Input . 19 Jitter . 19 Voltage Reference . 20 Digital Outputs 20 Over-Range Indicator . 20 Power Dissipation . 20 Nap/Sleep 20 Data Format 20 Clock Divider Synchronous Reset . 21 Serial Peripheral Interface 24 SPI Physical Interface 24 SPI Configuration 24 Device Information 24 Device Configuration/Control 25 Global Device Configuration/Control . 25 SPI Memory Map . 27 Equivalent Circuits . 30 A/D Evaluation Platform . 31 Layout Considerations 31 Split Ground and Power Planes 31 Clock Input Considerations 31 Exposed Paddle . 31 Bypass and Filtering . 31 LVDS Outputs . 31 LVCMOS Outputs 31 Unused Inputs 31 Definitions 31 Revision History 32 Package Outline Drawing 33 FN7982 Rev.4.0 Page 2 of 33 Jul 6, 2021