DATASHEET ISLA214S50 FN7973 Rev 2.00 14-Bit, 500/350 MSPS JESD204B High Speed Serial Output ADC April 25, 2013 The ISLA214S50 is a series of low-power, high-performance, Features 14-bit, analog-to-digital converters. Designed with JESD204A/B High Speed Data Interface FemtoCharge technology on a standard CMOS process, the series supports sampling rates of up to 500MSPS. The -JESD204A Compliant ISLA214S50 is part of a pin-compatible family of 12-, 14-, and - JESD204B Device Subclass 0 Compliant 16-bit A/Ds with maximum sample rates ranging from - JESD204B Device Subclass 2 Compatible 125MSPS to 500MSPS. The family minimizes power - Up to 3 JESD204 Output Lanes Running up to 4.375Gbps consumption while providing state-of-the-art dynamic - Highly Configurable JESD204 Transmitter performance. Multiple Chip Time Alignment and Deterministic Latency The device utilizes two time-interleaved 250MSPS unit ADCs to Support (JESD204B Device Subclass 2) achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all SPI Programmable Debugging Features and Test Patterns interleave clocking is managed internally. The proprietary 48-pin QFN 7mmx7mm Package Intersil Interleave Engine (I2E) performs automatic correction of offset, gain, and sample time mismatches between the unit Key Specifications ADCs to optimize performance. SNR 500/350MSPS The ISLA214S50 offers a highly configurable, JESD204B- 73.1/74.1 dBFS f = 30MHz IN compliant, high speed serial output link. The link offers data 71.0/71.6 dBFS f = 363MHz IN rates up to 4.375 Gbps per lane and multiple packing modes. The link can be configured to use two or three lanes to SFDR 500/350MSPS transmit the conversion data, allowing for flexibility in the 87/87 dBc f = 30MHz IN receiver design. The JESD204 transmitter also provides 78/81 dBc f = 363MHz IN deterministic latency and multi-chip time alignment support to satisfy complex synchronization requirements. Total Power Consumption: 1060mW 500MSPS A serial peripheral interface (SPI) port allows for extensive Applications configurability of the ADC and its JESD204B transmitter including access to its built-in link and transport-layer test Radar and Satellite Antenna Array Processing patterns as well as the programmable clock divider, enabling Broadband Communications and Microwave Receivers 2x harmonic clocking. High-Performance Data Acquisition The ISLA214S50 is available in a space-saving 7mmx7mm 48 Communications Test Equipment Ld QFN package. The package features a thermal pad for High-Speed Medical Imaging improved thermal performance and is specified over the full industrial temperature range (-40C to +85C) Pin-Compatible Family SPEED PRODUCT MODEL RESOLUTION (MSPS) AVAILABILITY ISLA214S50 14 500 Now ISLA214S35 14 350 Soon + FIGURE 1. SERDES DATA EYE AT 4.375Gbps FN7973 Rev 2.00 Page 1 of 41 April 25, 2013ISLA214S50 CLKP CLOCK GENERATION CLKN AINP 14-BIT LANE 2:0 P SHA 250MSPS AINN ADC LANE 2:0 N I2E VREF AND VCM JESD204 TRANSMITTER 14-BIT 250MSPS ADC VREF + 1.25V SPI CONTROL FIGURE 2. BLOCK DIAGRAM Pin Configuration ISLA214S50 (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VCM 1 36 OVDD AVDD 2 35 OVSS LANE2N AVSS 3 34 AVSS 4 33 LANE2P VINN OVSS 5 32 VINN 6 31 LANE1N VINP 7 30 LANE1P VINP 8 29 OVSS LANE0N AVSS 9 28 LANE0P AVSS 10 27 AVDD 11 26 OVSS PAD Exposed Paddle DNC 12 25 OVDD 13 14 15 16 17 18 19 20 21 22 23 24 FN7973 Rev 2.00 Page 2 of 41 April 25, 2013 RESETN DNC AVDD DNC NAPSLP AVDD AVDD NAPSLP CLKP AVSS AVDD CLKN CLKDIV AVSS (PLL) SYNCP SDIO SYNC SYNCN SCLK RESETN CSB DNC OVSS (PLL) SDO CSB SCLK OVDD (PLL) OVDD SDIO OVDD SDO (PLL) OVSS OVSS (PLL) OVSS OVDD OVSS OVDD (PLL)