ISLA222S12IR1Z Renesas

DATASHEET ISLA222S FN8302 Rev 1.00 Dual 12-bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC July 6, 2015 The ISLA222S is a series of low-power, high-performance, Features dual-channel 12-bit, analog-to-digital converters. Designed JESD204A/B high-speed data interface with FemtoCharge technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The -JESD204A compliant ISLA222S is part of a pin-compatible family of 12- and 14-bit - JESD204B device subclass 0 compliant dual-channel A/Ds with maximum sample rates ranging from - JESD204B device subclass 2 compatible 125MSPS to 250MSPS and shares the same analog core as - Up to 3 JESD204 output lanes running up to 4.375Gbps Intersil s proven ISLA222P series of ADCs. The family - Highly configurable JESD204 transmitter minimizes power consumption while providing state of the art dynamic performance, offering an optimal performance vs Multiple chip time alignment and deterministic latency power trade-off. support (JESD204B device subclass 2) SPI programmable debugging features and test patterns Differentiating the ISLA222S from the ISLA222P is its highly configurable, JESD204B-compliant, high-speed serial output 48-pin QFN 7mmx7mm package link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It can be configured to use one, two, Key Specifications or three lanes to transmit the conversion data, allowing for SNR at 250/200/125MSPS flexibility in the receiver design. The SERDES transmitter also provides deterministic latency and multi-chip time alignment 70.6/71.2/71.7 dBFS f = 30MHz IN support to satisfy an application s complex synchronization 70.3/70.7/70.9 dBFS f = 190MHz IN requirements. SFDR at 250/200/125MSPS A Serial Peripheral Interface (SPI) port allows for extensive 87/93/95 dBc f = 30MHz configurability of the JESD204B transmitter including access IN to its built-in link and transport layer test patterns. The SPI port 84/93/86 dBc f = 190MHz IN also provides control for numerous additional features including the fine gain and offset adjustments of the two ADC Total Power Consumption: 989mW at 250MSPS cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking. Applications Radar and satellite antenna array processing The ISLA222S is available in a space saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for Broadband communications and microwave receivers improved thermal performance and is specified over the full High-performance data acquisition industrial temperature range (-40C to +85C). Communications test equipment High-speed medical imaging Pin-compatible Family SPEED MODEL RESOLUTION (MSPS) ISLA224S25 14 250 ISLA224S20 14 200 ISLA224S12 14 125 ISLA222S25 12 250 ISLA222S20 12 200 ISLA222S12 12 125 FIGURE 1. SERDES DATA EYE AT 4.375Gbps FN8302 Rev 1.00 Page 1 of 38 July 6, 2015ISLA222S Table of Contents Block Diagram 3 Pin Configuration 3 Pin Descriptions . 4 Absolute Maximum Ratings . 5 Thermal Information . 5 Recommended Operating Conditions 5 Electrical Specifications . 5 Digital Specifications 8 Switching Specifications . 8 Typical Performance Curves . 10 Theory of Operation . 15 Functional Description . 15 Power-on Calibration . 15 User Initiated Reset 16 Temperature Calibration . 17 Analog Input 18 Clock Input . 18 Jitter . 19 Voltage Reference . 19 Digital Outputs 19 Power Dissipation . 19 Nap/Sleep 19 Data Format 20 Clock Divider Synchronous Reset . 20 Soft Reset . 20 JESD204 Transmitter 20 Overview . 20 Initial Lane Alignment 21 Test Patterns 22 Serial Peripheral Interface 26 SPI Physical Interface 26 SPI Configuration 27 Device Information 27 Device Configuration/Control 27 Global Device Configuration/Control . 28 ADDRESS 0xDF - 0xF3: JESD204 Registers 29 Address 0xDF-0xEE: JESD204 Parameter Interface . 29 SPI Memory Map . 31 Equivalent Circuits . 35 ADC Evaluation Platform 36 Layout Considerations 36 Split Ground and Power Planes 36 Clock Input Considerations 36 Exposed Paddle . 36 Bypass and Filtering . 36 CML Outputs 36 Unused Inputs 36 Definitions 36 Revision History 37 About Intersil 37 Package Outline Drawing 38 FN8302 Rev 1.00 Page 2 of 38 July 6, 2015