DATASHEET KAD5510P FN7693 Rev 3.00 Low Power 10-Bit, 250/210/170/125MSPS ADC February 8, 2016 The KAD5510P is a family of low power, high performance Features 10-bit analog-to-digital converters. Designed with Intersils 1.5GHz analog input bandwidth proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to 60fs clock jitter 250MSPS. The KAD5510P is part of a pin-compatible portfolio Programmable gain, offset and skew control of 10-, 12- and 14-bit A/Ds with sample rates ranging from Over-range indicator 125MSPS to 500MSPS. Selectable clock divider: 1, 2 or 4 A Serial Peripheral Interface (SPI) port allows for extensive configurability, as well as fine control of various parameters Clock phase selection such as gain and offset. Nap and sleep modes Digital output data is presented in selectable LVDS or CMOS Twos complement, gray code or binary data format formats. The KAD5510P is available in a 48 Ld QFN package DDR LVDS-compatible or LVCMOS outputs with an exposed paddle. Operating from a 1.8V supply, performance is specified across the industrial operating Programmable built-in test patterns temperature range (-40C to +85C). Single-supply 1.8V operation Pb-free (RoHS compliant) Key Specifications SNR = 60.7dBFS for f = 105MHz (-1dBFS) Applications IN SFDR = 86.1dBc for f = 105MHz (-1dBFS) Power amplifier linearization IN Total Power Consumption Radar and satellite antenna array processing - 234/189mW at 250/125MSPS (DDR Mode) Broadband communications High-performance data acquisition Related Literature Communications test equipment KAD5510P-50 datasheet, 10-Bit, 500MSPS A/D Converter WiMAX and microwave receivers CLKP CLKOUTP CLOCK GENERATION 0 CLKN CLKOUTN A = -1.0dBFS IN SNR = 60.7dBFS -20 (DDR) SFDR = 85.9dBc SINAD = 60.7dBFS D 4:0 P VINP 10-BIT -40 D 4:0 N DIGITAL SHA 250 MSPS ERROR ORP VINN ADC CORRECTION -60 ORN VCM LVDS/CMOS + OUTFMT 1.25V DRIVERS -80 SPI OUTMODE CONTROL -100 -120 0M 20M 40M 60M 80M 100M 120M FREQUENCY (Hz) FIGURE 2. SINGLE-TONE SPECTRUM AT 105MHz (250MSPS) FIGURE 1. FN7693 Rev 3.00 Page 1 of 31 February 8, 2016 NAPSLP AVDD AVSS CSB CLKDIV SCLK SDIO SDO OVDD OVSS AMPLITUDE (dBFS)KAD5510P Table of Contents Pin-Compatible Family . 3 Pin Configuration 3 Pin Descriptions . 4 Ordering Information 5 Absolute Maximum Ratings . 6 Thermal Information . 6 Recommended Operating Conditions 6 Digital Specifications 9 Timing Diagrams . 10 Switching Specifications 11 Typical Performance Curves . 12 Theory of Operation . 15 Functional Description . 15 Power-On Calibration . 15 User-Initiated Reset 16 Analog Input 16 VCM Output . 17 Clock Input . 17 Jitter . 17 Voltage Reference . 18 Digital Outputs 18 Over-Range Indicator . 18 Power Dissipation . 18 Nap/Sleep 18 Data Format 19 Serial Peripheral Interface 21 SPI Physical Interface 21 SPI Configuration 21 Device Information 22 Indexed Device Configuration/Control 22 Global Device Configuration/Control . 23 Device Test . 24 48-Pin Package Notes 24 SPI Memory Map 25 Equivalent Circuits . 27 ADC Evaluation Platform 28 Layout Considerations 28 PCB Layout Example . 28 Split Ground and Power Planes 28 Clock Input Considerations 28 Exposed Paddle . 28 Bypass and Filtering . 28 LVDS Outputs . 28 LVCMOS Outputs 28 Unused Inputs 28 General PowerPAD Design Considerations . 28 Definitions 29 Revision History 30 About Intersil 30 Package Outline Drawing 31 FN7693 Rev 3.00 Page 2 of 31 February 8, 2016