KAD5512HP-12Q48 Renesas

DATASHEET KAD5512HP FN6808 Rev 4.00 High Performance 12-Bit, 250/210/170/125MSPS ADC May 31, 2016 The KAD5512HP is the high performance member of the Features KAD5512 family of 12-bit analog-to-digital converters. Designed Pin-compatible with the KAD5512P Family, offering 2.2dB with Intersils proprietary FemtoCharge technology on a higher SNR standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5512HP is part of a pin-compatible Programmable gain, offset and skew control portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging 950MHz analog input bandwidth from 125MSPS to 500MSPS. 60fs Clock jitter A Serial Peripheral Interface (SPI) port allows for extensive Over-range indicator configurability, as well as fine control of various parameters such as gain and offset. Selectable clock divider: 1, 2 or 4 Clock phase selection Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512HP is available in 72 and 48 Ld QFN Nap and sleep modes packages with an exposed paddle. Operating from a 1.8V Twos complement, gray code or binary data format supply, performance is specified across the full industrial temperature range (-40C to +85C). DDR LVDS-compatible or LVCMOS outputs Programmable built-in test patterns Key Specifications Single-supply 1.8V operation SNR = 68.2dBFS for f = 105MHz (-1dBFS) IN Pb-free (RoHS compliant) SFDR = 81.1dBc for f = 105MHz (-1dBFS) IN Applications Power Consumption Power Amplifier linearization - 429/345mW at 250/125MSPS (SDR Mode) Radar and satellite antenna array processing - 390/309mW at 250/125MSPS (DDR Mode) Broadband communications High-performance data acquisition Communications test equipment WiMAX and microwave receivers CLKP CLKOUTP CLOCK GENERATION CLKN CLKOUTN D 11:0 P VINP 12-BIT D 11:0 N DIGITAL SHA 250 MSPS ERROR ORP VINN ADC CORRECTION ORN LVDS/CMOS VCM + OUTFMT 1.25V DRIVERS SPI OUTMODE CONTROL FIGURE 1. BLOCK DIAGRAM FN6808 Rev 4.00 Page 1 of 34 May 31, 2016 NAPSLP AVSS AVDD CSB CLKDIV SCLK SDIO SDO OVSS OVDDKAD5512HP Table of Contents Ordering Information 3 Absolute Maximum Ratings . 4 Thermal Information . 4 Operating Conditions 4 Electrical Specifications . 4 Digital Specifications 6 Timing Diagrams 7 Switching Specifications . 8 Pin Descriptions - 72 Ld QFN 9 Pin Configuration - 72 Ld QFN 11 Pin Descriptions - 48 Ld QFN . 12 Pin Configuration - 48 Ld QFN 13 Typical Performance Curves . 14 Theory of Operation . 17 Functional Description . 17 Power-On Calibration . 17 User-Initiated Reset 18 Analog Input 18 Clock Input . 19 Jitter . 20 Voltage Reference . 20 Digital Outputs 20 Over-Range Indicator . 20 Power Dissipation . 20 Nap/Sleep 20 Data Format 21 Serial Peripheral Interface 22 SPI Physical Interface 23 SPI Configuration 24 Device Information 24 Indexed Device Configuration/Control 24 Global Device Configuration/Control . 25 Device Test . 26 SPI Memory Map 27 Equivalent Circuits . 28 72 Ld/48 Ld Package Options 29 ADC Evaluation Platform 30 Layout Considerations 30 Split Ground and Power Planes 30 Clock Input Considerations 30 Exposed Paddle . 30 Bypass and Filtering . 30 LVDS Outputs . 30 LVCMOS Outputs 30 Unused Inputs 30 Definitions 30 Revision History 31 About Intersil 32 Package Outline Drawing 33 L48.7x7E . 33 L72.10x10D 34 FN6808 Rev 4.00 Page 2 of 34 May 31, 2016