DATASHEET KAD5512P FN6807 Rev 5.00 Low Power 12-Bit, 250/210/170/125MSPS ADC May 31, 2016 The KAD5512P is the low-power member of the KAD5512 Features family of 12-bit analog-to-digital converters. Designed with Half the power of the pin-compatible KAD5512HP family Intersils proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to 1.5GHz analog input bandwidth 250MSPS. The KAD5512P is part of a pin-compatible portfolio 60fs clock jitter of 10, 12 and 14-bit A/Ds with sample rates ranging from Programmable gain, offset and skew control 125MSPS to 500MSPS. Over-range indicator A Serial Peripheral Interface (SPI) port allows for extensive configurability, as well as fine control of various parameters Selectable clock divider: 1, 2 or 4 such as gain and offset. Clock phase selection Digital output data is presented in selectable LVDS or CMOS Nap and sleep modes formats. The KAD5512P is available in 72 Ld and 48 Ld QFN Twos complement, gray code or binary data format packages with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial SDR/DDR LVDS-compatible or LVCMOS outputs temperature range (-40C to +85C). Programmable built-in test patterns Single-supply 1.8V operation Key Specifications Pb-free (RoHS compliant) SNR = 66.1dBFS for f = 105MHz (-1dBFS) IN Applications SFDR = 87dBc for f = 105MHz (-1dBFS) IN Power amplifier linearization Total Power Consumption - 267/219mW at 250/125MSPS (SDR Mode) Radar and satellite antenna array processing - 234/189mW at 250/125MSPS (DDR Mode) Broadband communications High-performance data acquisition Related Literature Communications test equipment KAD5512P-50 Datasheet WiMAX and microwave receivers KAD5512HP, Datasheet 0 AIN = -1.0dBFS CLKP CLKOUTP SNR = 66.0dBFS CLOCK GENERATION -20 SFDR = 86.5dBc CLKN CLKOUTN SINAD = 65.9dBFS -40 D 11:0 P VINP 12-BIT D 11:0 N DIGITAL -60 SHA 250 MSPS ERROR ORP VINN ADC CORRECTION ORN -80 VCM LVDS/CMOS + OUTFMT 1.25V DRIVERS SPI OUTMODE CONTROL -100 -120 0 20 40 60 80 100 120 FREQUENCY (MHz) FIGURE 2. SINGLE-TONE SPECTRUM AT 105MHz (250MSPS) FIGURE 1. BLOCK DIAGRAM FN6807 Rev 5.00 Page 1 of 36 May 31, 2016 NAPSLP AVDD AVSS CSB CLKDIV SCLK SDIO SDO OVSS OVDD AMPLITUDE (dBFS)KAD5512P Table of Contents Ordering Information 3 Serial Peripheral Interface 24 SPI Physical Interface . 24 Pin Configuration 4 SPI Configuration . 24 Pin Descriptions - 72 Ld QFN 4 Device Information 25 Indexed Device Configuration/Control 25 Pin Configuration 7 Global Device Configuration/Control . 26 Pin Descriptions - 48 Ld QFN 7 Device Test 27 72 Ld/48 Ld Package Options 27 Absolute Maximum Ratings . 9 SPI Memory Map . 28 Thermal Information . 9 Equivalent Circuits . 29 Recommended Operating Conditions 9 ADC Evaluation Platform 31 Electrical Specifications . 9 Layout Considerations 31 Digital Specifications .12 PCB Layout Example 31 Timing Diagrams .13 Split Ground and Power Planes . 31 Clock Input Considerations . 31 Switching Specifications 14 Exposed Paddle . 31 Typical Performance Curves .15 Bypass and Filtering . 31 LVDS Outputs 31 Theory of Operation .18 LVCMOS Outputs 31 Functional Description . 18 Unused Inputs 31 Power-On Calibration . 18 General PowerPAD Design Considerations 31 User-Initiated Reset 19 Analog Input 19 Definitions 32 VCM Output . 20 Revision History . 33 Clock Input . 20 Jitter . 20 About Intersil 34 Voltage Reference . 21 Package Outline Drawing . 35 Digital Outputs 21 L48.7x7E 35 Over Range Indicator . 21 L72.10x10D . 36 Power Dissipation . 21 Nap/Sleep 21 Data Format 22 FN6807 Rev 5.00 Page 2 of 36 May 31, 2016