Datasheet KAD5514P 14-Bit, 250/210/170/125MSPS ADC The KAD5514P (KAD5514P-12, KAD5514P-17, Features KAD5514P-21, KAD5514P-25) is a family of Programmable gain, offset, and skew control low-power, high performance 14-bit, analog-to-digital 950MHz analog input bandwidth converters. The family is designed with the proprietary FemtoCharge technology on a standard CMOS 60fs clock jitter process, and supports sampling rates of up to Over-range indicator 250MSPS. The KAD5514P is part of a pin-compatible portfolio of 10, 12, and 14-bit ADCs with sample rates Selectable clock divider: 1, 2, or 4 ranging from 125MSPS to 500MSPS. Clock phase selection A Serial Peripheral Interface (SPI) port allows for Nap and sleep modes extensive configurability and fine control of various Twos complement, gray code or binary data format parameters such as gain and offset. DDR LVDS-compatible or LVCMOS outputs Digital output data is presented in selectable LVDS or CMOS formats. The KAD5514P is available in 72 Ld Programmable built-in test patterns and 48 Ld QFN packages with an exposed paddle. Single-supply 1.8V operation The devices operate from a 1.8V supply, and Pb-free (RoHS compliant) performance is specified across the full industrial temperature range (-40C to +85C). Key Specifications Applications SNR = 69.4dBFS for f = 105MHz (-1dBFS) IN Power amplifier linearization SFDR = 82.2dBc for f = 105MHz (-1dBFS) IN Radar and satellite antenna array processing Total power consumption Broadband communications 429/345mW at 250/125MSPS (SDR Mode) High-performance data acquisition 390/309mW at 250/125MSPS (DDR Mode) Communications test equipment Related Literature WiMAX and microwave receivers For a full list of related documents, visit our website: KAD5514P-12, KAD5514P-17, KAD5514P-21, KAD5514P-25 device pages CLKP CLKOUTP Clock Generation CLKN CLKOUTN D 13:0 P VINP 14-Bit D 13:0 N Digital SHA 250 MSPS Error ORP ADC VINN Correction ORN VCM LVDS/CMOS + OUTFMT 1.25V Drivers SPI OUTMODE Control Figure 1. Block Diagram FN6804 Rev.4.00 Page 1 of 44 Jun.17.19 NAPSLP AVSS AVDD CSB CLKDIV SCLK SDIO SDO OVSS OVDDKAD5514P Contents 1. Overview . 4 1.1 Ordering Information . 4 1.2 Pin Configurations . 5 1.3 Pin Descriptions . 6 2. Specifications 10 2.1 Absolute Maximum Ratings . 10 2.2 Thermal Information . 10 2.3 Electrical Specifications 11 2.4 Digital Specifications 13 2.5 Timing Diagrams . 14 2.6 Switching Specifications . 14 3. Typical Performance Curves 16 4. Theory of Operation . 19 4.1 Functional Description . 19 4.2 Power-On Calibration . 19 4.3 User-Initiated Reset . 20 4.4 Analog Input . 21 4.5 Clock Input 22 4.6 Jitter . 23 4.7 Voltage Reference 23 4.8 Digital Outputs . 23 4.9 Over-Range Indicator . 24 4.10 Power Dissipation 24 4.11 Nap/Sleep 24 4.12 Data Format . 25 5. Serial Peripheral Interface 27 5.1 SPI Physical Interface . 27 5.2 SPI Configuration . 29 5.3 Device Information 29 5.4 Indexed Device Configuration/Control . 30 5.5 Global Device Configuration/Control 31 5.6 Device Test . 33 5.7 SPI Memory Map . 34 6. Equivalent Circuits . 36 7. Layout Considerations 38 7.1 Split Ground and Power Planes 38 7.2 Clock Input Considerations . 38 7.3 Exposed Paddle 38 7.4 Bypass and Filtering 38 7.5 LVDS Outputs . 38 7.6 LVCMOS Outputs 38 7.7 Unused Inputs . 38 7.8 72 Ld/48 Ld Package Options . 38 FN6804 Rev.4.00 Page 2 of 44 Jun.17.19