DATASHEET KAD5610P FN6810 Rev 3.00 Dual 10-Bit, 250/210/170/125MSPS A/D Converter May 31, 2016 The KAD5610P is a family of low-power, high performance, Features dual-channel 10-bit, analog-to-digital converters. Designed Programmable gain, offset and skew control with Intersils proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of 1.3GHz analog input bandwidth up to 250MSPS. The KAD5610P-25 is the fastest member of 60fs clock jitter this pin-compatible family, which also features sample rates of Over-range indicator 210MSPS (KAD5610P-21), 170MSPS (KAD5610P-17) and 125MSPS (KAD5610P-12). Selectable clock divider: 1, 2 or 4 A Serial Peripheral Interface (SPI) port allows for extensive Clock phase selection configurability, as well as fine control of gain, skew and offset Nap and sleep modes matching between the two converter cores. Twos complement, gray code or binary data format Digital output data is presented in selectable LVDS or CMOS DDR LVDS compatible or LVCMOS outputs formats. The KAD5610P is available in a 72 Ld QFN package with an exposed paddle. Performance is specified over the full Programmable built-in test patterns industrial temperature range (-40C to +85C). Single-supply 1.8V operation Pb-free (RoHs compliant) Key Specifications Applications SNR = 60.7dBFS for f = 105MHz (-1dBFS) IN Power amplifier linearization SFDR = 86.1dBc for f = 105MHz (-1dBFS) IN Radar and satellite antenna array processing Power consumption - 411mW at 250MSPS Broadband communications - 327mW at 125MSPS High-performance data acquisition Communications test equipment WiMAX and microwave receivers CLKP CLKOUTP CLOCK GENERATION CLKN CLKOUTN AINP 10-BIT D 9:0 P SHA 250MSPS ADC AINN D 9:0 N VREF ORP DIGITAL VCM ERROR ORN CORRECTION OUTFMT BINP 10-BIT SHA 250MSPS OUTMODE BINN ADC VREF + 1.25V SPI CONTROL FIGURE 1. BLOCK DIAGRAM FN6810 Rev 3.00 Page 1 of 30 May 31, 2016 NAPSLP AVSS AVDD CLKDIV RESETN CSB SCLK SDIO SDO OVSS OVDDKAD5610P Table of Contents Key Specifications . 1 Ordering Information 3 Absolute Maximum Ratings . 4 Thermal Information . 4 Recommended Operating Conditions 4 Electrical Specifications . 4 Digital Specifications 6 Timing Diagrams 7 Switching Specifications . 8 Pin Descriptions . 9 Typical Performance Curves . 12 Theory of Operation . 15 Functional Description . 15 Power-On Calibration . 15 User-Initiated Reset 16 Analog Input 16 Clock Input . 17 Jitter . 17 Voltage Reference . 18 Digital Outputs 18 Over-Range Indicator . 18 Power Dissipation . 18 Nap/Sleep 18 Data Format 19 Serial Peripheral Interface 21 SPI Physical Interface 21 SPI Configuration 22 Device Information 22 Indexed Device Configuration/Control 22 Global Device Configuration/Control . 23 Device Test . 24 SPI Memory Map 25 Equivalent Circuits . 26 ADC Evaluation Platform 27 Layout Considerations 27 Split Ground and Power Planes 27 Clock Input Considerations 27 Exposed Paddle . 27 Bypass and Filtering . 27 LVDS Outputs . 27 LVCMOS Outputs 27 Unused Inputs 28 Definitions 28 Revision History 29 About Intersil 29 Package Outline Drawing 30 FN6810 Rev 3.00 Page 2 of 30 May 31, 2016