DATASHEET KAD5612P FN6803 Rev 3.00 Dual 12-Bit, 250/210/170/125MSPS A/D Converter May 26, 2016 The KAD5612P is a family of low-power, high-performance, Features dual-channel 12-bit, analog-to-digital converters. Designed Programmable gain, offset and skew control with FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The 1.3GHz analog input bandwidth KAD5612P-25 is the fastest member of this pin-compatible 60fs clock jitter family, which also features sample rates of 210MSPS Over-range indicator (KAD5612P-21), 170MSPS (KAD5612P-17) and 125MSPS (KAD5612P-12). Selectable clock divider: 1, 2 or 4 A Serial Peripheral Interface (SPI) port allows for extensive Clock phase selection configurability, as well as fine control of gain, skew and offset Nap and sleep modes matching between the two converter cores. Twos complement, gray code or binary data format Digital output data is presented in selectable LVDS or CMOS DDR LVDS-compatible or LVCMOS outputs formats. The KAD5612P is available in a 72 Ld QFN package with an exposed paddle. Performance is specified over the full Programmable built-in test patterns industrial temperature range (-40C to +85C). Single-supply 1.8V operation Pb-free (RoHS compliant) Key Specifications Applications SNR = 66.0dBFS for f = 105MHz (-1dBFS) IN Power amplifier linearization SFDR = 86.0dBc for f = 105MHz (-1dBFS) IN Radar and satellite antenna array processing Power consumption - 429mW at 250MSPS Broadband communications - 342mW at 125MSPS High-performance data acquisition Communications test equipment WiMAX and microwave receivers CLKP CLKOUTP CLOCK GENERATION CLKN CLKOUTN AINP 12-BIT D 11:0 P SHA 250MSPS AINN ADC D 11:0 N VREF ORP DIGITAL VCM ERROR ORN CORRECTION OUTFMT BINP 12-BIT SHA 250MSPS OUTMODE BINN ADC VREF + 1.25V SPI CONTROL FIGURE 1. BLOCK DIAGRAM FN6803 Rev 3.00 Page 1 of 29 May 26, 2016 NAPSLP AVSS AVDD CLKDIV RESETN CSB SCLK SDIO SDO OVSS OVDDKAD5612P Table of Contents Ordering Information 3 Absolute Maximum Ratings . 4 Thermal Information . 4 Electrical Specifications . 4 Digital Specifications 6 Timing Diagrams 7 Switching Specifications . 7 Pin Descriptions . 8 Pin Configuration . 10 Typical Performance Curves . 11 Theory of Operation . 14 Functional Description . 14 Power-On Calibration . 14 User-Initiated Reset 15 Analog Input 15 Clock Input . 16 Jitter . 16 Voltage Reference . 17 Digital Outputs 17 Over-Range Indicator . 17 Power Dissipation . 17 Nap/Sleep 17 Data Format 18 Serial Peripheral Interface 19 SPI Physical Interface 19 SPI Configuration 21 Device Information 21 Indexed Device Configuration/Control 21 Global Device Configuration/Control . 22 Device Test . 23 SPI Memory Map 24 Equivalent Circuits . 25 ADC Evaluation Platform 26 Layout Considerations 26 Split Ground and Power Planes 26 Clock Input Considerations 26 Exposed Paddle . 26 Bypass and Filtering . 26 LVDS Outputs . 27 LVCMOS Outputs 27 Unused Inputs 27 Definitions 27 Revision History 28 About Intersil 28 Package Outline Drawing 29 FN6803 Rev 3.00 Page 2 of 29 May 26, 2016