USERS MANUAL KAD-FMC-EVALZ AN1665 Rev 0.00 FMC ADC Evaluation Board September 30, 2011 Hardware High-Speed ADC Evaluation There are two components in the hardware portion of the Platform evaluation platform: the daughter card and the motherboard Interfaces Intersils High-Speed ADC Evaluation PCB Family (Figure 1). The ADC is contained on the daughter card, which to FMC Based Evaluation Platforms routes power from the motherboard and contains the analog 40MSPS to 500MSPS Operation input circuitry, clock drive and decoupling. The daughter card interfaces to the motherboard through a mezzanine connector. SPI Access for ADC Configuration The motherboard provides power to the ADCs analog and Compatible with all Intersil High-Speed ADC Daughter Cards digital supply pins from separate LDOs from Intersils High performance linear regulator family. The ADCs digital outputs Evaluation Platform Overview are routed through the mezzanine connector to the FMC connector at the motherboard card edge. Intersils FMC based high-speed ADC evaluation platform The user must supply low-jitter RF generators for the clock and consists of custom designed hardware, which allows analog inputs. Recommendations of suitable generators can interfacing to an FMC based FPGA evaluation platform. This be found in Appendix A: RF Generators on page 2. allows for direct FPGA processing of the ADC output data and system prototyping for a user. SPI access to the ADC is Many low-jitter RF generators exhibit high harmonic spectral possible at the FMC connector or optionally at a separate content relative to the ADC performance. A band-pass filter is header on the PCB (JP3). recommended to attenuate the harmonics. A wideband attenuator in series with the band-pass filter is also recommended for daughter cards without on-board attenuators. Current spikes from the ADCs switched capacitor sample-and-hold amplifier can create signal reflections in the coaxial cable. The attenuator reduces these reflections and improves performance. Software There is no software provided with the evaluation system. Data capture and ADC performance verification needs to be done at the receiving FPGA. A reset of the ADC is possible at switch S1 on the PCB. FIGURE 1. EVALUATION PLATFORM BLOCK DIAGRAM AN1665 Rev 0.00 Page 1 of 9 September 30, 2011KAD-FMC-EVALZ Initial Start-Up JP3 Referring to Figure 1, connect the daughter card to the motherboard by aligning the two mating mezzanine connectors. 1 Four screws on the motherboard (not shown) align with mounting holes in the daughter card. The FMC connector should be aligned and connected with an appropriate mating FMC-based FPGA FIGURE 3. JP3 PINOUT evaluation system. Next, connect the RF generators to the Clock and Analog input SMA connectors. Set the clock frequency as SPI Programming desired with the power level at +10dBm. Similarly, set the analog Access to the ADC SPI port is available at both the FMC input frequency with a power level of approximately +7dBm (the connector and header JP3. The ADCs typically support both full-scale value will vary depending on the loss of the input path 3-wire and 4-wire SPI communication and the default mode at and gain of the ADC). With the RF generators on, apply +5V power-up is 3-wire mode (consult the appropriate ADC data sheet power supply to the motherboard. The daughter card is powered for more information). It is recommended to use 4-wire SPI by Intersil linear regulators on the motherboard. communication with the FMC based ADC motherboard, requiring that the ADC first be placed in 4-wire SPI mode by writing to the Daughter Cards appropriate ADC register (consult data sheet). A resistor on the Each daughter card is designed to produce optimal ADC daughter card (R4) at the CPLD will need to be removed. Logic performance and simplify the evaluation process. Some boards levels for the SPI port on card is 3.3V LVCMOS (level translation have multiple connections for the analog input and clock. For to 1.8V is done on the ADC daughter cards). example, low-frequency and high-frequency input paths are provided on certain boards. A high-frequency input path may Appendix A: RF Generators have a balun interface, while a low frequency path may use a Intersil uses the following RF generators as clock and signal transformer or buffer amplifier (for DC-coupling). sources when characterizing high-speed ADCs: Rohde & Schwarz: SMA100A Motherboard Agilent: 8644B (with Low-Noise option) The only connection required for the motherboard is +5V power at J1 (5V wall supply is supplied), JP1 is an optional connection. These generators provide very low jitter to optimize the SNR The data outputs are LVDS and will require 100 differential performance of the ADC under test. Other generators with similar termination resistors at the receiver/FPGA phase noise performance can also be used. Contact Intersil Technical Support for recommendations. Appendix B: Daughter Cards The FMC ADC Evaluation Board (KAD-FMC-EVALZ) connects data, clock, and SPI control signals to/from an ADC to an external FPGA through an LPC FMC connector and a 180 pin Molex connector. The Molex connector interfaces with any of the KAD5XXX and ISLAXXX ADC daughtercards. The schematic for the respective Intersil ADC daughtercard can be downloaded from our website for additional information and bit-ordering. Note that the MSB bit-ordering is different for the ISLA2XXX and KAD5XXX,ISL1XXP50 families. Additional information on Intersil ADC Daughter Cards can be found at the respective ADC product pages on our website. FIGURE 2. PCB TOP VIEW AN1665 Rev 0.00 Page 2 of 9 September 30, 2011 GND MISO SCLK MOSI GND CSB