Datasheet
RL78/G13 R01DS0131EJ0330
Rev.3.30
RENESAS MCU
Mar 31, 2016
True Low Power Platform (as low as 66 A/MHz, and 0.57 A for RTC + LVD), 1.6 V to 5.5 V
operation, 16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications
1. OUTLINE
1.1 Features
Ultra-low power consumption technology DMA (Direct Memory Access) controller
VDD = single power supply voltage of 1.6 to 5.5 V 2/4 channels
HALT mode Number of clocks during transfer between 8/16-bit
SFR and internal RAM: 2 clocks
STOP mode
SNOOZE mode
Multiplier and divider/multiply-accumulator
16 bits 16 bits = 32 bits (Unsigned or signed)
RL78 CPU core
32 bits 32 bits = 32 bits (Unsigned)
CISC architecture with 3-stage pipeline
16 bits 16 bits + 32 bits = 32 bits (Unsigned or
Minimum instruction execution time: Can be changed
signed)
from high speed (0.03125 s: @ 32 MHz operation
with high-speed on-chip oscillator) to ultra-low speed
Serial interface
(30.5 s: @ 32.768 kHz operation with subsystem
CSI: 2 to 8 channels
clock)
UART/UART (LIN-bus supported): 2 to 4 channels
Address space: 1 MB
2 2
I C/Simplified I C communication: 2 to 8 channels
General-purpose registers: (8-bit register 8) 4
banks
Timer
On-chip RAM: 2 to 32 KB
16-bit timer: 8 to 16 channels
12-bit interval timer: 1 channel
Code flash memory
Real-time clock: 1 channel (calendar for 99
Code flash memory: 16 to 512 KB
years, alarm function, and
Block size: 1 KB
clock correction function)
Prohibition of block erase and rewriting (security
Watchdog timer: 1 channel (operable with the
function)
dedicated low-speed on-chip
On-chip debug function
oscillator)
Self-programming (with boot swap function/flash
shield window function)
A/D converter
8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
Data Flash Memory
Analog input: 6 to 26 channels
Data flash memory: 4 KB to 8 KB
Internal reference voltage (1.45 V) and temperature
Back ground operation (BGO): Instructions can be
Note 1
sensor
executed from the program memory while rewriting
the data flash memory.
I/O port
Number of rewrites: 1,000,000 times (TYP.)
I/O port: 16 to 120 (N-ch open drain I/O [withstand
Voltage of rewrites: VDD = 1.8 to 5.5 V
voltage of 6 V]: 0 to 4, N-ch open drain I/O
Note 2
[VDD withstand voltage /EVDD withstand
High-speed on-chip oscillator Note 3
voltage ]: 5 to 25)
Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8
Can be set to N-ch open drain, TTL input buffer, and
MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
on-chip pull-up resistor
High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20
Different potential interface: Can connect to a
to +85C)
1.8/2.5/3 V device
On-chip key interrupt function
Operating ambient temperature
On-chip clock output/buzzer output controller
TA = -40 to +85C (A: Consumer applications, D:
Industrial applications )
Others
TA = -40 to +105C (G: Industrial applications)
On-chip BCD (binary-coded decimal) correction
circuit
Power management and reset function
On-chip power-on-reset (POR) circuit
Notes 1. Can be selected only in HS (high-speed
On-chip voltage detector (LVD) (Select interrupt and
main) mode
reset from 14 levels)
2. Products with 20 to 52 pins
3. Products with 64 to 128 pins
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
R01DS0131EJ0330 Rev.3.30 Page 1 of 196
Mar 31, 2016
RL78/G13 1. OUTLINE
ROM, RAM capacities
Flash Data RAM RL78/G13
ROM flash 20 pins 24 pins 25 pins 30 pins 32 pins 36 pins
128 8 KB 12 R5F100AG R5F100BG R5F100CG
KB KB
R5F101AG R5F101BG R5F101CG
96 8 KB 8 KB R5F100AF R5F100BF R5F100CF
KB
R5F101AF R5F101BF R5F101CF
64 4 KB 4 KB R5F1006E R5F1007E R5F1008E R5F100AE R5F100BE R5F100CE
Note
KB R5F1016E R5F1017E R5F1018E R5F101AE R5F101BE R5F101CE
48 4 KB 3 KB R5F1006D R5F1007D R5F1008D R5F100AD R5F100BD R5F100CD
Note
KB
R5F1016D R5F1017D R5F1018D R5F101AD R5F101BD R5F101CD
32 4 KB 2 KB R5F1006C R5F1007C R5F1008C R5F100AC R5F100BC R5F100CC
KB R5F1016C R5F1017C R5F1018C R5F101AC R5F101BC R5F101CC
16 4 KB 2 KB R5F1006A R5F1007A R5F1008A R5F100AA R5F100BA R5F100CA
KB
R5F1016A R5F1017A R5F1018A R5F101AA R5F101BA R5F101CA
Flash Data RAM RL78/G13
ROM flash
40 pins 44 pins 48 pins 52 pins 64 pins 80 pins 100 pins 128 pins
512 8 KB 32 KB R5F100FLR5F100GL R5F100JL R5F100LL R5F100ML R5F100PL R5F100SL
Note
KB
R5F101FLR5F101GL R5F101JL R5F101LL R5F101ML R5F101PL R5F101SL
384 8 KB 24 KB R5F100FKR5F100GKR5F100JKR5F100LKR5F100MK R5F100PK R5F100SK
KB
R5F101FKR5F101GKR5F101JKR5F101LKR5F101MK R5F101PK R5F101SK
256 8 KB 20 KB R5F100FJR5F100GJ R5F100JJ R5F100LJ R5F100MJ R5F100PJ R5F100SJ
Note
KB
R5F101FJR5F101GJ R5F101JJ R5F101LJ R5F101MJ R5F101PJ R5F101SJ
192 8 KB 16 KB R5F100EH R5F100FH R5F100GH R5F100JH R5F100LH R5F100MH R5F100PH R5F100SH
KB
R5F101EH R5F101FH R5F101GH R5F101JH R5F101LH R5F101MH R5F101PH R5F101SH
128 8 KB 12 KB R5F100EG R5F100FG R5F100GG R5F100JG R5F100LG R5F100MG R5F100PG
KB R5F101EG R5F101FG R5F101GG R5F101JG R5F101LG R5F101MG R5F101PG
96 8 KB 8 KB R5F100EF R5F100FF R5F100GF R5F100JF R5F100LF R5F100MF R5F100PF
KB
R5F101EF R5F101FF R5F101GF R5F101JF R5F101LF R5F101MF R5F101PF
64 4 KB 4 KB R5F100EE R5F100FE R5F100GE R5F100JE R5F100LE
Note
KB
R5F101EE R5F101FE R5F101GE R5F101JE R5F101LE
Note
48 4 KB R5F100ED R5F100FD R5F100GD R5F100JD R5F100LD
3 KB
KB
R5F101ED R5F101FD R5F101GD R5F101JD R5F101LD
32 4 KB 2 KB R5F100EC R5F100FC R5F100GC R5F100JC R5F100LC
KB
R5F101EC R5F101FC R5F101GC R5F101JC R5F101LC
16 4 KB 2 KB R5F100EA R5F100FA R5F100GA
KB
R5F101EA R5F101FA R5F101GA
Note The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L): Start address FF300H
R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L): Start address FEF00H
R5F100xJ, R5F101xJ (x = F, G, J, L, M, P): Start address FAF00H
R5F100xL, R5F101xL (x = F, G, J, L, M, P, S): Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for
RL78 Family (R20UT2944).
R01DS0131EJ0330 Rev.3.30 Page 2 of 196
Mar 31, 2016