Datasheet R01DS0282EJ0240 RL78/G11 Rev.2.40 RENESAS MCU Oct 30, 2020 True low-power platform (58.3 A/MHz, and 0.64 A for operation with only LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16-Kbyte code flash memory, and 33 DMIPS at 24 MHz 1. OUTLINE 1.1 Features Ultra-low power consumption technology High-speed on-chip oscillator VDD = 1.6 V to 5.5 V Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 HALT mode MHz STOP mode High accuracy: 1.0% (VDD = 1.8 to 5.5 V, TA = - SNOOZE mode 20 to +85C) RL78 CPU core Middle-speed on-chip oscillator CISC architecture with 3-stage pipeline Selectable from 4 MHz, 2 MHz, and 1 MHz. Minimum instruction execution time: Can be changed from high speed (0.04167 s: 24 Operating ambient temperature MHz operation with high-speed on-chip TA = -40 to +85C (A: Consumer applications) oscillator) to ultra-low speed (66.6 s: 15 kHz TA = -40 to +105C (G: Industrial applications) operation with low-speed on-chip oscillator clock) Power management and reset function Multiply/divide/multiply & accumulate On-chip power-on-reset (POR) circuit instructions are supported. On-chip voltage detector (LVD) (Select interrupt Address space: 1 Mbytes and reset from 14 levels) General-purpose registers: (8-bit register 8) 4 banks Data transfer controller (DTC) On-chip RAM: 1.5 Kbytes Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode Code flash memory Activation sources: Activated by interrupt Code flash memory: 16 Kbytes sources. Block size: 1 Kbytes Chain transfer function On-chip debug function Self-programming (with boot swap function/flash Event link controller (ELC) shield window function) Event signals of 18 types can be linked to the specified peripheral function. Data flash memory Data flash memory: 2 Kbytes Serial interfaces Back ground operation (BGO): Instructions can CSI: 4 channels be executed from the program memory while UART: 2 channel rewriting the data flash memory. 2 2 I C/simplified I C: 4 channels Number of rewrites: 1,000,000 times (TYP.) 2 Multimaster I C: 2 channels Voltage of rewrites: VDD = 1.8 to 5.5 V R01DS0282EJ0240 Rev.2.40 Page 1 of 143 Oct 30, 2020RL78/G11 1. OUTLINE Timers PGA 16-bit timer (TAU): 4 channels 1 channels TKB: 1 channel I/O ports 12-bit interval timer: 1 channel I/O port: 17 to 21 (N-ch open drain I/O VDD 8-bit interval timer: 2 channels Note 1 withstand voltage /EVDD withstand Watchdog timer: 1 channel Note 2 voltage : 10 to 14) Can be set to N-ch open drain, TTL input buffer, A/D converter and on-chip pull-up resistor 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 Different potential interface: Can connect to a V) 1.8/2.5/3.0 V device Analog input: 10 to 11 channels On-chip key interrupt function Internal reference voltage (1.45 V) and On-chip clock output/buzzer output controller temperature sensor Others D/A converter On-chip BCD (binary-coded decimal) correction circuit 8/10-bit resolution D/A converter (VDD = 1.6 to 5.5 V) On-chip data operation circuit Analog input: 2 channels (channel 1: output to the Note 1. 16, 20, 24-pin products ANO1 pin, channel 0: output to the comparator) Note 2. 25-pin products Output voltage: 0 V to VDD Real-time output function Remark The functions mounted depend on the product. See 1.6 Outline of Functions. Comparator 2 channels Operating modes: Comparator high-speed mode, comparator low-speed mode, window mode ROM, RAM capacities RL78/G11 Flash Data RAM ROM flash 25 10 pins 16 pins 20 pins 24 pins pins 1.5 16 KB 2 KB R5F1051A R5F1054A R5F1056A R5F1057A R5F1058A KB Remark The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F105xA (x = 1, 4, 6, 7, 8): Start address FF900H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0282EJ0240 Rev.2.40 Page 2 of 143 Oct 30, 2020