Datasheet RL78/I1A R01DS0171EJ0210 Rev.2.10 RENESAS MCU Jul 31, 2013 True Low Power Platform (as low as 156.25 A/MHz, and 0.60 A for RTC + LVD), 2.7 V to 5.5 V operation, 32 to 64 Kbyte Flash, for Lighting Control Applications 1. OUTLINE 1.1 Features Ultra-Low Power Technology 16-bit timers KB0 to KB2, and KC0 for PWM output 2.7 V to 5.5 V operation from a single supply 16-bit timers KB0 to KB2: maximum 6 outputs (3 ch 2) Stop (RAM retained): 0.23 A, (LVD enabled): 0.31 Smooth start function, dithering function, forced output A stop function (unsyncronized with comparator or Halt (RTC + LVD): 0.60 A external interrupt), and interleave PFC function Operating: 156.25 A/MHz Average resolution < 1 nsec output, 64 MHz (when 16-bit RL78 CPU Core using PLL) + dithering option Delivers 41 DMIPS at maximum operating frequency 16-bit timer KC0 (3 ch) of 32 MHz PWM output gating function by interlocking with 16- Instruction Execution: 86% of instructions can be executed in 1 to 2 clock cycles bit timers KB0, KB1, and KB2 CISC Architecture (Harvard) with 3-stage pipeline Multiply Signed & Unsigned: 16 x 16 to 32-bit result in Extended-Function Timers 1 clock cycle Multi-function 16-bit timers: Up to 8 channels MAC: 16 x 16 to 32-bit result in 2 clock cycles Real-time clock (RTC): 1 channel (full calendar and 16-bit barrel shifter for shift & rotate in 1 clock cycle alarm function with watch correction function) 1-wire on-chip debug function Interval Timer: 12-bit, 1 channel 15 kHz watchdog timer : 1 channel (window function) Main Flash Memory Density: 32 KB to 64 KB Multiple Communication Interfaces 2 Block size: 1 KB Up to 1 x I C multi-master (SM/PM bus support) On-chip single voltage flash memory with protection Up to 1 x CSI/SPI (7-, 8-bit) from block erase/writing Up to 3 x UART (7-, 8-, 9-bit), DALI Support 1ch Self-programming with secure boot swap function Up to 1 x LIN and flash shield window function Rich Analog Data Flash Memory ADC: Up to 11 channels, 8/10-bit resolution, 2.125 s Data Flash with background operation conversion time Data flash size: 4 KB Supports 2.7 V Erase Cycles: 1 Million (typ.) Internal voltage reference (1.45 V) Erase/programming voltage: 2.7 V to 5.5 V Comparator: Up to 6 channels, Internal DAC 3ch 8bit resolution, window comparator mode PGA (x4 to x32):6 input RAM On-chip temperature sensor 2 KB to 4 KB size options Supports operands or instructions Back-up retention in all modes Safety Features (IEC or UL 60730 compliance) Flash memory CRC calculation RAM parity error check High-speed On-chip Oscillator RAM/SFR write protection 32 MHz with +/ 1% accuracy over voltage (2.7 V to Illegal memory access detection 5.5 V) and temperature (20 C to 85 C) Clock stop/ frequency detection Pre-configured settings: 32 MHz, 24 MHz, 16 MHz, ADC self-test 12 MHz, 8 MHz, 4 MHz & 1 MHz General Purpose I/O Reset and Supply Management 5V tolerant, high-current (up to 8.5 mA per pin) Power-on reset (POR) monitor/generator Open-Drain, Internal Pull-up support Low voltage detection (LVD) with 6 setting options (Interrupt and/or reset function) Operating Ambient Temperature Standard: 40 C to +105 C Data Memory Access (DMA) Controller Extend: 40 C to +125 C Up to 2 fully programmable channels <R> Transfer unit: 8- or 16-bit Package Type and Pin Count SSOP: 20, 30, 38 R01DS0171EJ0210 Rev.2.10 Page 1 of 105 Jul 31, 2013 RL78/I1A 1. OUTLINE ROM, RAM capacities Flash ROM Data flash RAM RL78/I1A 20 pins 30 pins 38 pins Note 64 KB 4 KB 4 KB R5F107AE R5F107DE 32 KB 4 KB 2 KB R5F1076C R5F107AC Note This is about 3 KB when the self-programming function and data flash function are used. R01DS0171EJ0210 Rev.2.10 Page 2 of 105 Jul 31, 2013