Datasheet R01DS0244EJ0230 RL78/I1D Rev. 2.30 RENESAS MCU Jun 30, 2020 True low-power platform (58.3 A/MHz, and 0.64 A for operation with only RTC2 and LVD) for the general- purpose applications, with 1.6-V to 3.6-V operation, 8- to 32-Kbyte code flash memory, and 33 DMIPS at 24 MHz 1. OUTLINE 1.1 Features Ultra-low power consumption technology Data transfer controller (DTC) Transfer modes: Normal transfer mode, repeat transfer VDD = 1.6 V to 3.6 V mode, block transfer mode HALT mode Activation sources: Activated by interrupt sources. STOP mode Chain transfer function SNOOZE mode Event link controller (ELC) RL78 CPU core Event signals of 20 types can be linked to the specified CISC architecture with 3-stage pipeline peripheral function. Minimum instruction execution time: Can be changed from high speed (0.04167 s: 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (66.6 Serial interfaces s: 15 kHz operation with low-speed on-chip <R> CSI: 1 or 2 channels oscillator clock) UART: 1 channel Multiply/divide/multiply & accumulate instructions are 2 2 I C/simplified I C: 1 or 2 channels supported. Address space: 1 MB Timers General-purpose registers: (8-bit register 8) 4 banks 16-bit timer: 4 channels On-chip RAM: 0.7 to 3 KB 12-bit interval timer: 1 channel 8-bit interval timer: 4 channels Code flash memory Real-time clock: 1 channel (calendar for 99 years, alarm Code flash memory: 8 to 32 KB function, and clock correction function) Block size: 1 KB Watchdog timer: 1 channel Prohibition of block erase and rewriting (security function) A/D converter On-chip debug function 8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V) Self-programming (with boot swap function/flash shield Analog input: 6 to 17 channels window function) Internal reference voltage (1.45 V) and temperature sensor Data flash memory Data flash memory: 2 KB Comparator Back ground operation (BGO): Instructions can be 2 channels executed from the program memory while rewriting the Operating modes: Comparator high-speed mode, data flash memory. comparator low-speed mode, window mode Number of rewrites: 1,000,000 times (TYP.) Voltage of rewrites: VDD = 1.8 to 3.6 V Operational amplifier 4 channels High-speed on-chip oscillator Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 I/O ports MHz, 3 MHz, 2 MHz, and 1 MHz High accuracy: 1.0% (VDD = 1.8 to 3.6 V, TA = -20 to I/O port: 14 to 42 (N-ch open drain I/O withstand +85C) voltage of 6 V : 4, N-ch open drain I/O VDD withstand voltage : 3 to 7) Can be set to N-ch open drain, TTL input buffer, and on- Middle-speed on-chip oscillator chip pull-up resistor Selectable from 4 MHz, 2 MHz, and 1 MHz. Different potential interface: Can connect to a 1.8/2.5 V device Operating ambient temperature On-chip key interrupt function TA = -40 to +105C (G: Industrial applications) On-chip clock output/buzzer output controller Others Power management and reset function On-chip BCD (binary-coded decimal) correction circuit On-chip power-on-reset (POR) circuit On-chip data operation circuit On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels) Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01DS0244EJ0230 Rev. 2.30 Page 1 of 101 Jun 30, 2020RL78/I1D 1. OUTLINE ROM, RAM capacities RL78/I1D Flash Data flash RAM ROM 30 32 20 pins 24 pins pins pins 48 pins Note 32 KB 2 KB R5F117AC R5F117BC R5F117GC 3 KB 16 KB 2 KB 2 KB R5F1176A R5F1177A R5F117AA R5F117BA R5F117GA 8 KB 2 KB 0.7 KB R5F11768 R5F11778 R5F117A8 Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F117xC (x = A, B, G): Start address FF300H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0244EJ0230 Rev. 2.30 Page 2 of 101 Jun 30, 2020