Datasheet R01DS0246EJ0112 RL78/G1F Rev.1.12 RENESAS MCU Apr 28, 2021 True Low Power Platform (as low as 66 A/MHz, and 0.57 A for RTC + LVD), 1.6 V to 5.5 V operation, 32/64 Kbyte Flash, Max.32 MHz CPU operation, Enhanced analog functions, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-low power consumption technology Serial interfaces CSI: 3 to 6 channels VDD = single power supply voltage of 1.6 to 5.5 V which UART/UART (LIN-bus supported): 3 channels can operate a 1.8 V device at a low voltage 2 2 I C/simplified I C: 3 to 6 channels HALT mode IrDA: 1 channel STOP mode SNOOZE mode Timer 16-bit timer: 9 channels RL78 CPU core (Timer Array Unit (TAU): 4 channels, Timer RJ: 1 CISC architecture with 3-stage pipeline channel, Timer RD: 2 channels (with PWMOPA), Minimum instruction execution time: Can be changed Timer RG: 1 channel, Timer RX: 1 channel) from high speed (0.03125 s: 32 MHz operation with 12-bit interval timer: 1 channel high-speed on-chip oscillator) to ultra-low speed (30.5 Real-time clock: 1 channel (calendar for 99 years, alarm s: 32.768 kHz operation with subsystem clock) function, and clock correction function) Multiply/divide/multiply & accumulate instructions are Watchdog timer: 1 channel (operable with the dedicated supported. low-speed on-chip oscillator) Address space: 1 MB General-purpose registers: (8-bit register 8) 4 banks A/D converter On-chip RAM: 5.5 KB 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V) Analog input: 8 to 17 channels Code flash memory Internal reference voltage (1.45 V) and temperature Code flash memory: 32/64 KB sensor Block size: 1 KB Prohibition of block erase and rewriting (security D/A converter function) 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V) On-chip debug function Analog output: 1 or 2 channels Self-programming (with boot swap function/flash shield Output voltage: 0 V to VDD window function) Real-time output function Data flash memory Comparator Data flash memory: 4 KB 2 channels (pin selector is provided for 1 channel) Back ground operation (BGO): Instructions can be Incorporates a function for the output of a timer window executed from the program memory while rewriting the in combination with the timer array unit. data flash memory. The external reference voltage or internal reference Number of rewrites: 1,000,000 times (TYP.) voltage can be selected as the reference voltage. Voltage of rewrites: VDD = 1.8 to 5.5 V Programmable gain amplifier (PGA) High-speed on-chip oscillator 1 channel Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz, I/O port 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz I/O port: 20 to 58 (N-ch open drain I/O withstand High accuracy: 1.0% (VDD = 1.8 to 5.5 V, TA = -20 to voltage of 6 V : 2 to 4, N-ch open drain I/O VDD +85C) withstand voltage/EVDD withstand voltage : 10 to 16) Can be set to N-ch open drain, TTL input buffer, and on- Operating ambient temperature chip pull-up resistor TA = 40 to +85C (A: Consumer applications) Different potential interface: Can connect to a 1.8/2.5/3 TA = 40 to +105C (G: Industrial applications) V device Power management and reset function On-chip key interrupt function On-chip power-on-reset (POR) circuit On-chip clock output/buzzer output controller On-chip voltage detector (LVD) (Select interrupt and Others reset from 14 levels) On-chip BCD (binary-coded decimal) correction circuit Data transfer controller (DTC) Transfer modes: Normal transfer mode, repeat transfer Remark The functions mounted depend on the mode, block transfer mode product. See 1.6 Outline of Functions. Activation sources: Activated by interrupt sources. Chain transfer function Event link controller (ELC) Event signals of 22 types can be linked to the specified peripheral function. R01DS0246EJ0112 Rev.1.12 Page 1 of 143 Apr 28, 2021RL78/G1F 1. OUTLINE ROM, RAM capacities RL78/G1F Flash ROM Data flash RAM 24 pins 32 pins 36 pins 48 pins 64 pins Note 64 KB 4 KB 5.5 KB R5F11B7E R5F11BBE R5F11BCE R5F11BGE R5F11BLE Note 32 KB 4 KB 5.5 KB R5F11B7C R5F11BBC R5F11BCC R5F11BGC R5F11BLC Note This is about 4.5 KB when performing self-programming and rewriting the data flash memory (For details, see CHAPTER 3 CPU ARCHITECTURE in the RL78/G1F Users Manual). R01DS0246EJ0112 Rev.1.12 Page 2 of 143 Apr 28, 2021