Datasheet R01DS0274EJ0110 RL78/I1E Rev. 1.10 RENESAS MCU Jun 30, 2016 1. OUTLINE 1.1 Features Ultra-low power consumption technology High-speed on-chip oscillator VDD= 2.4 to 5.5 V Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz HALT mode High accuracy: STOP mode 2.0% (VDD = 2.4 to 5.5 V, TA = 40 to +105 C) SNOOZE mode 3.0% (VDD = 2.4 to 5.5 V, TA = 40 to +125 C) RL78 CPU core Operating ambient temperature CISC architecture with 3-stage pipeline TA = 40 to +105C (G: Industrial applications) Minimum instruction execution time: Can be changed TA = 40 to +125C (M: Industrial applications) from high speed (0.03125 s: 32 MHz operation Note with high-speed on-chip oscillator or PLL clock) to Power management and reset function ultra-low speed (1 s: 1 MHz operation with high- On-chip power-on-reset (POR) circuit speed on-chip oscillator or PLL clock) On-chip voltage detector (LVD) (Select interrupt and Multiply/divide/multiply & accumulate instructions are reset from 7 levels) supported. Address space: 1 MB Data transfer controller (DTC) General-purpose registers: (8-bit register 8) 4 Transfer modes: Normal transfer mode, repeat transfer banks mode, block transfer mode On-chip RAM: 8 KB Activation sources: Activated by interrupt sources. Chain transfer function Note For industrial applications (M TA = 40 to +125 C): 0.04167 s 24 MHz operation Event link controller (ELC) with high-speed on-chip oscillator or PLL Event signals of 16 types can be linked to the specified clock peripheral function. Code flash memory Serial interfaces Code flash memory: 32 KB CSI: 2 channels Block size: 1 KB UART: 2 channels (UART with LIN-bus supported: 1 Prohibition of block erase and rewriting (security channel) function) 2 2 I C/simplified I C: 2 channels On-chip debug function Self-programming (with boot swap function/flash shield Timer window function) 16-bit timer: 8 channels (Timer Array Unit (TAU): 6 channels, timer RJ: 1 Data flash memory channel, timer RG: 1 channel) Data flash memory: 4 KB Interval timer: 1 channel Back ground operation (BGO): Instructions can be Real-time clock: 1 channel (calendar for 99 years, executed from the program memory while rewriting the alarm function, and clock correction function) data flash memory. Watchdog timer: 1 channel (operable with the Number of rewrites: 1,000,000 times (TYP.) dedicated low-speed on-chip oscillator) Voltage of rewrites: VDD = 2.4 to 5.5 V Analog front-end (AFE) power supply Sensor power supply (SBIAS) output: 0.5 V to 2.2 V R01DS0274EJ0110 Rev. 1.10 Page 1 of 108 Jun 30, 2016RL78/I1E 1. OUTLINE 24-bit A/D converter with programmable gain D/A converter instrumentation amplifier 12-bit R-2R resistor ladder type D/A converter (AVDD = 24-bit second-order A/D converter (AVDD = 2.7 to 2.7 to 5.5 V) 5.5 V) Analog output: 1 channel (via configurable amplifier) SNDR: 85 dB (TYP.) I/O port Output data rate: 488 sps to 15.625 ksps in normal mode CMOS I/O: 10 to 14 (N-ch open drain I/O withstanding 61 sps to 1.953 ksps in low power mode voltage of VDD : 6, CMOS I/O: 7 to 11, CMOS input: 3) Programmable gain instrumentation amplifier input: 3 Can be set to TTL input buffer and on-chip pull-up or 4 channels resistor (differential input mode or single-ended input mode Different potential interface: Can connect to a 2.5/3 V can be specified for each input channel) device DAC for offset adjustment On-chip clock output/buzzer output controller Variable gain: x1 to x64 Others On-chip temperature sensor On-chip BCD (binary-coded decimal) correction circuit 10-bit A/D converter 8-bit/10-bit successive approximation A/D converter (AVDD = 2.7 to 5.5 V) Analog input: 8 or 10 channels, sensor power supply (SBIAS), and internal reference voltage Internal reference voltage (1.45 V) Configurable amplifier Matrix configuration that consists of 3 operational amplifier channels and a configurable switch (AVDD = 2.7 to 5.5 V) Can be used as a 2- or 3-channel general operational amplifier Operational amplifier output: 3 channels General-purpose Analog I/O ports: 5 or 6 channels Offset voltage calibration ROM, RAM capacities RL78/I1E Flash ROM Data flash RAM 32 pins 36 pins 32 KB 4 KB 8 KB R5F11CBC R5F11CCC R01DS0274EJ0110 Rev. 1.10 Page 2 of 108 Jun 30, 2016