Datasheet R01DS0318EJ0100 RL78/H1D Rev. 1.00 RENESAS MCU Apr 13, 2018 Analog front-end (24-bit A/D converter with programmable gain instrumentation amplifier, Amplifier unit and 12-bit D/A converter), External signal sampler/Sampling output timer detector and Integrated LCD controller/driver. True Low Power Platform (as low as 70.8 A/MHz, and 0.68 A in Halt mode( RTC2 + LVD)), 1.8 V to 5.5V operation, 64 to 128 Kbyte Flash, 33 DMIPS at 24 MHz, for Healthcare and Flow meter applications. 1. OUTLINE 1.1 Features Background operation (BGO): Instructions Ultra-low power consumption technology can be executed from the program memory VDD = 2.4 to 5.5 V while rewriting the data flash memory. (10-bit SAR A/D converter: 2.4 to 5.5 V, Number of rewrites: 1,000,000 times (TYP.) operating voltage of the analog front-end Note 1 Note 1 Voltage of rewrites: VDD = 2.4 to 5.5 V , (AFE): 2.7 to 5.5 V) , Note 2 Note 2 1.8 to 5.5 V VDD = 1.8 to 5.5 V HALT mode High-speed on-chip oscillator STOP mode Select from 24 MHz, 16 MHz, 12 MHz, 8 SNOOZE mode MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz RL78 CPU core High accuracy: 1.0% (VDD = 2.4 to 5.5 V, TA CISC architecture with 3-stage pipeline Note 1 = -20 to +85C , VDD = 1.8 to 5.5 V, TA = Minimum instruction execution time: Can be Note 2 -20 to +85C ) changed from high speed (0.04167 s: 24 MHz operation with high-speed on-chip Operating ambient temperature oscillator clock) to ultra-low speed (30.5 s: TA = -40 to +85C (A: Consumer 32.768 kHz operation with subsystem Note 1 applications , D: Industrial clock) Note 2 applications ) Multiply/divide and multiply/accumulate instructions are supported. Address space: 1 MB Power management and reset function General-purpose registers: (8-bit register 8) On-chip power-on-reset (POR) circuit 4 banks On-chip voltage detector (LVD) (Select Note 1 Note 2 Note 1 Note 2 On-chip RAM: 5.5 KB , 8 KB interrupt and reset from 9 or 12 levels) Code flash memory Code flash memory: 64 to 128 KB Data transfer controller (DTC) Block size: 1 KB Transfer modes: Normal transfer mode, Prohibition of block erase and rewriting repeat transfer mode, block transfer mode (security function) Activation sources: Activated by interrupt On-chip debug function sources (35 sources). Self-programming (with boot swap Chain transfer function function/flash shield window function) Event link controller (ELC) Data flash memory Event signals of 18 to 26 types can be linked Data flash memory: 4 KB to the specified peripheral function. R01DS0318EJ0100 Rev. 1.00 Page 1 of 143 Apr 13, 2018RL78/H1D 1. OUTLINE - D/A converter for offset adjustment Serial interfaces - Variable gain: x1 to x64 CSI/CSI (SPI supported): 3 channels UART/UART (LIN-bus supported):3 channels 2 2 Amplifier unit (R5F11N and R5F11P only) I C/simplified I C: 4 channels Programmable gain instrumentation amplifier Serial interface UARTMG (9600 bps 38.4 (PGA1): 1 channel (R5F11NL, R5F11PL, and kHz): 1 channel (R5F11R only) R5F11NG only) - Analog input: 1 or 2 channels Timers - Variable gain: x12, x16, x20, x24 16-bit timer: Rail-to-rail operational amplifier (AMP0): 1 Timer array unit (TAU): 8 channels, channel Timer RJ: 2 channels (R5F11R only) General-purpose operational amplifier Note 1 Note 2 8-bit timer:2 channels , 6 channels (AMP1, AMP2): 2 channels (R5F11NL, 12-bit interval timer: 1 channel R5F11PL, and R5F11NG only) Real-time clock 2: 1 channel (calendar for 99 years, alarm function, and clock correction D/A converter (R5F11N and R5F11P only) function) 8-bit resolution R-2R resistor ladder D/A Watchdog timer: 1 channel (operable with the converter (DAC0) (AVDD = 2.7 to 5.5 V): dedicated low-speed on-chip oscillator) 1 channel External signal sampler: 1 channel (R5F11R 12-bit resolution R-2R resistor ladder D/A only) converter (DAC1) (AVDD = 2.7 to 5.5 V): Sampling output timer detector (SMOTD): 1 channel (R5F11NL, R5F11PL, and 6 channels for input, 3 channels for output R5F11NG only) (R5F11R only) 10-bit SAR A/D converter LCD controller/driver 10-bit resolution A/D converter (VDD = 2.4 to Internal voltage boosting method, capacitor Note 1 Note 2 5.5 V , VDD = 1.8 to 5.5 V ) split method, and external resistance division Analog input: 3 channels method are switchable. Note 4 Segment signal output: Internal reference voltage (TYP. 1.45 V) Note 3 Note 4 27 (23) to 36 (32) and temperature sensor Note 3 Common signal output: 4 (8) I/O ports I/O ports: 29 to 63 (N-ch open drain I/O Analog front-end power supply circuit withstand voltage of 6 V : 2) (R5F11N and R5F11P only) Can be set to N-ch open drain, TTL input AFE reference power supply (ABGR) buffer, and on-chip pull-up resistor LDO for supplying power to internal circuits On-chip clock output/buzzer output controller (REGA) LDO for supplying power to a sensor (SBIAS): 0.5 to 2.2 V Others On-chip BCD (binary-coded decimal) correction circuit 24-bit A/D converter with programmable gain instrumentation amplifier (R5F11N and R5F11P Note 1. In case of R5F11N and R5F11P. only) Note 2. In case of R5F11R. 24-bit second-order A/D converter (AVDD Note 3. The number in parentheses indicates = 2.7 to 5.5 V) the number of signal outputs when 8 - SNDR: 85 dB (TYP.) coms are used. - Output data rate: 488 sps to 15.625 ksps in Note 4. Selectable only in HS (high-speed normal mode main) mode. 61 sps to 1.953 ksps in low power mode Programmable gain instrumentation amplifier Remark The functions mounted depend on the (PGA0) product. See 1.6 Outline of Functions. - Analog input: 1 to 5 channels (differential input mode or single-ended input mode) R01DS0318EJ0100 Rev. 1.00 Page 2 of 143 Apr 13, 2018