Datasheet R01DS0193EJ0200 RL78/G12 Rev.2.00 RENESAS MCU Sep 06, 2013 True Low Power Platform (as low as 63 A/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications 1. OUTLINE 1.1 Features <R> Ultra-Low Power Technology Data Memory Access (DMA) Controller 1.8 V to 5.5 V operation from a single supply Up to 2 fully programmable channels Stop (RAM retained): 0.23 A, (LVD enabled): 0.31 A Transfer unit: 8- or 16-bit Snooze: 0.7 mA (UART), 1.20 mA (ADC) Operating: 63 A /MHz Multiple Communication Interfaces 2 Up to 3 x I C master 2 16-bit RL78 CPU Core Up to 1 x I C multi-master Delivers 31 DMIPS at maximum operating frequency Up to 3 x CSI/SPI (7-, 8-bit) of 24 MHz Up to 3 x UART (7-, 8-, 9-bit) Instruction Execution: 86 % of instructions can be executed in 1 to 2 clock cycles Extended-Function Timers CISC Architecture (Harvard) with 3-stage pipeline Multi-function 16-bit timers: Up to 8 channels Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle Interval Timer: 12-bit, 1 channel MAC: 16 x 16 to 32-bit result in 2 clock cycles 15 kHz watchdog timer : 1 channel (window function) 16-bit barrel shifter for shift & rotate in 1 clock cycle 1-wire on-chip debug function Rich Analog ADC: Up to 11 channels, 10-bit resolution, 2.1 s Main Flash Memory conversion time Density: 2 KB to 16 KB Supports 1.8 V to 5.5 V Block size: 1 KB Internal voltage reference (1.45 V) On-chip single voltage flash memory with protection On-chip temperature sensor from block erase/writing Safety Features (IEC or UL 60730 compliance) Data Flash Memory Flash memory CRC calculation Data Flash with background operation RAM parity error check Data flash size: 2 KB size options RAM write protection Erase Cycles: 1 Million (typ.) SFR write protection Erase/programming voltage: 1.8 V to 5.5 V Illegal memory access detection Clock stop/ frequency detection RAM ADC self-test 256 B to 1.5 KB size options Supports operands or instructions General Purpose I/O Back-up retention in all modes 5 V tolerant, high-current (up to 20 mA per pin) Open-Drain, Internal Pull-up support High-speed Oscillator Oscillator 24MHz with +/- 1% accuracy over voltage (1.8 V to Operating Ambient Temperature 5.5 V) and temperature (-20 C to 85 C) Standard: 40 C to +85 C Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, Extended: 40 C to +105 C 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz Package Type and Pin Count Reset and Supply Management QFN: 24 Power-on reset (POR) monitor/generator SSOP: 20, 30 Low voltage detection (LVD) with 12 setting options (Interrupt and/or reset function) * There is difference in specifications between every product. Please refer to specification for details. R01DS0193EJ0200 Rev.2.00 Page 1 of 106 Sep 06, 2013 RL78/G12 1. OUTLINE ROM, RAM capacities Code flash Data flash RAM 20 pins 24 pins 30 pins 16 KB 2 KB 2 KB R5F102AA R5F103AA Note 1 Note 1 2 KB 1.5 KB R5F1026A R5F1027A Note 1 Note 1 R5F1036A R5F1037A Note 1 Note 1 12 KB 2KB 1 KB R5F10269 R5F10279 R5F102A9 Note 1 Note 1 R5F10369 R5F10379 R5F103A9 Note 1 Note 1 8 KB 2 KB 768 B R5F10268 R5F10278 R5F102A8 Note 1 Note 1 R5F10368 R5F10378 R5F103A8 4 KB 2KB 512 B R5F10267 R5F10277 R5F102A7 R5F10367 R5F10377 R5F103A7 Note 2 2 KB 2 KB 256 B R5F10266 Note 2 R5F10366 Notes 1. This is 640 bytes when the self-programming function or data flash function is used. (For details, see CHAPTER 3 CPU ARCHITECTURE in the RL78/G12 Users Manual Hardware.) 2. The self-programming function cannot be used for R5F10266 and R5F10366. Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual. R01DS0193EJ0200 Rev.2.00 Page 2 of 106 Sep 06, 2013