Datasheet R01DS0202EJ0120 RX110 Group Rev.1.20 Renesas MCUs Jul 29, 2016 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, up to 5 comms channels, 12-bit A/D, RTC Features PLQP0064KB-A 10 10 mm, 0.5 mm pitch PLQP0064GA-A 14 14 mm, 0.8 mm pitch 32-bit RX CPU core PLQP0048KB-A 7 7 mm, 0.5 mm pitch 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz Accumulator handles 64-bit results (for a single instruction) from 32-bit 32-bit operations PWQN0048KB-A 7 7 mm, 0.5 mm pitch Multiplication and division unit handles 32-bit 32-bit PWQN0040KC-A 6 6 mm, 0.5 mm pitch operations (multiplication instructions take one CPU clock cycle) PWLG0064KA-A 5 5 mm, 0.5 mm pitch Fast interrupt PWLG0036KA-A 4 4 mm, 0.5 mm pitch CISC Harvard architecture with five-stage pipeline Variable-length instruction format, ultra-compact code Independent watchdog timer (WDT) On-chip debugging circuit 15-kHz on-chip oscillator produces a dedicated clock Low power consumption functions signal to drive IWDT operation. Operation from a single 1.8 to 3.6 V supply On-chip functions for IEC 60730 compliance Three low power modes Supply current Clock frequency accuracy measurement circuit, IWDT, High-speed operating mode: 0.1 mA/MHz functions to assist in RAM testing, etc. Software standby mode: 0.35 A Up to five channels for communication Recovery time from software standby mode: 4.8 s SCI: Asynchronous mode, clock synchronous mode, On-chip flash memory for code, no wait states smart card interface (up to seven channels) 2 Operation at 32 MHz, read cycle of 31.25 ns I C bus interface: Transfer at up to 400 kbps, capable of No wait states for reading at full CPU speed SMBus operation (one channel) 8 to 128 Kbyte capacities RSPI: Up to 16 Mbps (one channel) Programmable at 1.8 V Up to 6 extended-function timers For instructions and operands 16-bit MTU: Input capture/output compare, On-chip SRAM, no wait states phase counting mode (four channels) 8 to 16 Kbyte capacities 16-bit CMT (two channels) Data transfer controller (DTC) 12-bit A/D converter Four transfer modes Up to 14 channels Transfer can be set for each interrupt source. 1.0 s minimum conversion speed Double trigger (data duplication) function for motor Reset and power supply voltage management control Six types including the power-on reset (POR) Temperature sensor Low voltage detection (LVD) with voltage settings Clock functions General I/O ports External clock input frequency: Up to 20 MHz 5-V tolerant, open drain, input pull-up Main clock oscillator frequency: 1 to 20 MHz Multi-function pin controller (MPC) Sub-clock oscillator frequency: 32.768 kHz Low-speed on-chip oscillator: 4 MHz Multiple I/O pins can be selected for peripheral functions. High-speed on-chip oscillator: 32 MHz1% ( 20 to 85C) Unique ID IWDT-dedicated on-chip oscillator: 15 kHz 32-byte ID code for the MCU Generate a dedicated 32.768-kHz clock for the RTC On-chip clock frequency accuracy measurement circuit Operating temperature range (CAC) 40 to 85C Real-time clock (RTC) 40 to 105C 30-second, leap year, and error adjustment functions Calendar count mode or binary count mode selectable Capable initiating exit from software standby mode R01DS0202EJ0120 Rev.1.20 Page 1 of 108 Jul 29, 2016RX110 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/3) Classification Module/Function Description CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per one clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit 32-bit 64-bit On-chip divider: 32-bit 32-bit 32 bits Barrel shifter: 32 bits Memory ROM Capacity: 8 K /16 K /32 K /64 K /96 K /128 Kbytes 32 MHz, no-wait memory access Programming/erasing method: Serial programming (asynchronous serial communication), self-programming RAM Capacity: 8 K /10 K /16 Kbytes 32 MHz, no-wait memory access MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, and IWDT-dedicated on-chip oscillator Oscillation stop detection: Available Clock frequency accuracy measurement circuit (CAC) Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 32 MHz (at max.) Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32, 64). Resets RES pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt (LVDAa) is generated. Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels Low power Low power consumption Module stop function consumption functions Three low power consumption modes Sleep mode, deep sleep mode, and software standby mode Function for lower operating Operating power control modes power consumption High-speed operating mode, middle-speed operating mode, and low-speed operating mode Interrupt Interrupt controller (ICUb) Interrupt vectors: 65 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins) Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt) 16 levels specifiable for the order of priority DMA Data transfer controller Transfer modes: Normal transfer, repeat transfer, and block transfer (DTCa) Activation sources: Interrupts Chain transfer function R01DS0202EJ0120 Rev.1.20 Page 2 of 108 Jul 29, 2016