Datasheet
RX210 Group
R01DS0041EJ0150
Renesas MCUs
Rev.1.50
Oct 18, 2013
50-MHz 32-bit RX MCUs, 78 DMIPS, up to 1-MB flash memory,
12-bit A/D, 10-bit D/A, ELC, MPC, RTC, up to 15 comms channels;
incorporating functions for IEC60730 compliance
Features
PLQP0144KA-A 20 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 14 mm, 0.5-mm pitch
32-bit RX CPU core
PLQP0080KB-A 12 12 mm, 0.5-mm pitch
Max. operating frequency: 50 MHz
PLQP0064KB-A 10 10 mm, 0.5-mm pitch
PLQP0048KB-A 7 7 mm, 0.5-mm pitch
Capable of 78 DMIPS in operation at 50 MHz
PLQP0080JA-A 14 14 mm, 0.65-mm pitch
Accumulator handles 64-bit results (for a single instruction)
PLQP0064GA-A 14 14 mm, 0.8-mm pitch
from 32- 32-bit operations
Multiplication and division unit handles 32- 32-bit
operations (multiplication instructions take one CPU clock PTLG0145KA-A 7 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 7 mm, 0.65-mm pitch
cycle)
PTLG0100KA-A 5.5 5.5 mm, 0.5-mm pitch
Fast interrupt
PTLG0064JA-A 6 6 mm, 0.65-mm pitch
CISC Harvard architecture with 5-stage pipeline SWBG0069LA-A 3.91 4.26mm,
0.40-mm pitch
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Useful functions for IEC60730 compliance
Low power design and architecture
Self-diagnostic and disconnection-detection assistance
Operation from a single 1.62-V to 5.5-V supply
functions for the A/D converter, clock frequency accuracy
1.62-V operation available (at up to 20 MHz)
measurement circuit, independent watchdog timer, functions
Deep software standby mode with RTC remaining usable
to assist in RAM testing, etc.
Four low power consumption modes
Up to 15 communications channels
On-chip flash memory for code, no wait states
SCI with many useful functions (up to 13 channels)
50-MHz operation, 20-ns read cycle
Asynchronous mode, clock synchronous mode, smart card
No wait states for reading at full CPU speed
interface
64-K to 1-Mbyte capacities
2
I C bus interface: Transfer at up to 400 kbps, capable of
User code programmable via the SCI
SMBus operation (one channel)
Programmable at 1.62 V
RSPI (one channel): Transfer at up to 16 Mbps (768-Kbyte/
For instructions and operands
1-Mbyte flash memory or 144/145-pin products)
On-chip data flash memory
External address space
8 Kbytes
Four CS areas (4 16 Mbytes)
(Number of times of reprogramming: 100,000)
8- or 16-bit bus space is selectable per area
Erasing and programming impose no load on the CPU.
Up to 20 extended-function timers
On-chip SRAM, no wait states
16-bit MTU: input capture, output compare, complementary
12-K to 96-Kbyte size capacities
PWM output, phase counting mode
(six channels)
DMA
16-bit TPU: input capture, output capture, phase counting
DMAC: Incorporates four channels
mode (six channels)
DTC: Four transfer modes
8-bit TMR (four channels)
ELC
16-bit compare-match timers (four channels)
Module operation can be initiated by event signals without
12-bit A/D converter
going through interrupts.
Capable of conversion within 1 s
Modules can operate while the CPU is sleeping.
Sample-and-hold circuits (for three channels)
Reset and supply management
Three-channel synchronized sampling available
Nine types of reset, including the power-on reset (POR) Self-diagnostic function and analog input disconnection
Low voltage detection (LVD) with voltage settings
detection assistance function
Clock functions
10-bit D/A converter
Frequency of external clock: Up to 20 MHz
Analog comparator
Frequency of the oscillator for sub-clock generation: 32.768
kHz
General I/O ports
PLL circuit input: 4 MHz to 12.5 MHz
5-V tolerant, open drain, input pull-up, switching of driving
On-chip low- and high-speed oscillators, dedicated on-chip
ability
low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
MPC
Clock frequency accuracy measurement circuit (CAC)
Multiple locations are selectable for I/O pins of peripheral
functions
Realtime clock
Adjustment functions (30 seconds, leap year, and error) Temperature sensor
Year and month display or 32-bit second display (binary
Operating temp. range
counter) is selectable
40 C to +85C
Time capture function
40 C to +105 C
Time capture on event-signal input through external pins
RTC capable of initiating return from deep software standby
Applications
mode
69WLBGA (SWBG0069LA-A): General consumer
Independent watchdog timer equipment
Other than above package: General industrial and consumer
125-kHz on-chip oscillator produces a dedicated clock signal
equipment
to drive IWDT operation.
R01DS0041EJ0150 Rev.1.50 Page 1 of 221
Oct 18, 2013RX210 Group 1. Overview
1.Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
This product includes chip version A (part no.: R5F5210xAxxx), chip version B (part no.: R5F5210xBxxx), and chip
version C (part no: R5F5210xCxxx).
For the specification differences between chip versions A, B, and C, see Table 1, Specification Differences
Depending on Chip Versions.
Table 1.1 Outline of Specifications (1 / 5)
Classification Module/Function Description
CPU CPU
Maximum operating frequency: 50 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory ROM
Capacity: 64 K/96 K/128 K/256 K/384 K/512 K/768 Kbytes/1 Mbyte
50 MHz, no-wait memory access
On-board programming: 3 types
Off-board programming
RAM
Capacity: 12 K/16 K/20 K/32 K/64 K/96 Kbytes
50 MHz, no-wait memory access
E2 DataFlash
Capacity: 8 Kbytes
Number of times for programming/erasing: 100,000
MCU operating mode Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode
(software switching)
Clock Clock generation circuit
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator
Oscillation stop detection
Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock
(BCLK), and FlashIF clock (FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 50 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
Devices connected to the external bus run in synchronization with the external bus clock (BCLK):
12.5 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FlashIF clock (FCLK): 32 MHz (at max.)
Reset RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, deep software standby reset, and software reset
Voltage detection Voltage detection circuit
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
(LVDAa)
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
R01DS0041EJ0150 Rev.1.50 Page 2 of 221
Oct 18, 2013