Features
DATASHEET
RX63T Group
Renesas MCUs R01DS0087EJ0100
Rev.1.00
Aug 28, 2012
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, 12-bit ADC
(3 S/H circuits, double data register, amplifier, comparator): two units, 10-bit ADC one unit, the three ADC units are capable
of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary channels and four single-phase
complementary channels or three three-phase complementary channels and one single-phase complementary channel)
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU
PLQP0064KB-A 10 10mm, 0.5mm pitch
clock cycle)
PLQP0048KB-A 7 x 7mm, 0.5mm pitch
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Up to five communications interfaces
Variable-length instructions: Ultra-compact code
SCI with multiple functionalities (up to 3 channels)
Supports the memory protection unit (MPU)
Choose from among asynchronous mode, clock-synchronous
Two types of debugging interfaces: JTAG and FINE (two-line)
2
mode, smart-card interface mode, simple SPI, simple I C, and
Low-power design and architecture
extended serial mode.
Operation from a single 2.7- to 3.6-V supply
2
I C bus interface for transfer at up to 400 kbps (1 channels)
Four low-power modes
RSPI for high-speed transfer (1 channels)
On-chip main flash memory, no wait states
Up to 16 extended-function timers
100-MHz operation, 10-ns read cycle (no wait states)
16-bit MTU3: 100-MHz operation, input capture, output compare,
64-Kbyte/48-Kbyte/32-Kbyte capacities
two three-phase complementary PWM output channels,
User code is programmable by on-board or off-board
complementary PWM imposing no load on the CPU, phase-
programming.
counting mode
100-MHz operation, input capture, output compare, four
On-chip data flash memory
complementary single-phase PWM output channels, or one three-
8 Kbytes, reprogrammable up to 100,000 times
phase complementary PWM output channel and one single-phase
Programming/erasing as background operations (BGOs)
complementary PWM output channel, complementary PWM
On-chip SRAM, no wait states
imposing no load on the CPU, operation linked with comparator
(for counting and control of PWM-signal negation), detection of
8-Kbyte capacities
For instructions and operands abnormal oscillation frequencies (for IEC 60730 compliance) (4
channels)
Can provide backup on deep software standby
16-bit compare-match timers (4 channels)
DMA
12-bit A/D converter for 1-MHz operation, with 8
DMAC: Incorporates four channels
channels
DTC
Up to 3 12-bit channels, and incorporating 1 sample-and-hold
Reset and supply management
circuits
Power-on reset (POR)
Self-diagnosis (for IEC60730 compliance)
Low voltage detection (LVD) with voltage settings
ADC: Three sample-and-hold circuits, double data registers,
comparators (on 3 channels)
Clock functions
External crystal oscillator or internal PLL for operation at 8 to
Register write protection function can protect
12.5 MHz values in important registers against overwriting.
Internal 125-kHz LOCO
Up to 48 pins for GPIO
Dedicated 125-kHz LOCO for the IWDT
5-V tolerance, open drain, input pull-up
Clock frequency accuracy measurement circuit (CAC)
Operating temp. range
Independent watchdog timer
40 C to +85 C
125-kHz LOCO clock operation
Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
R01DS0087EJ0100 Rev.1.00 Page 1 of 76
Aug 28, 2012RX63T Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the ROM capacity. For details, see Table 1.2, Functions of RX63T
Group Products.
Table 1.1 Outline of Specifications (1/4)
Classification Module/Function Description
CPU CPU Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU Single precision floating point (32-bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory ROM Capacity: 64/48/32 Kbytes.
100 MHz, no-wait access
On-board programming: 2 types
RAM Capacity: 8 Kbytes
100 MHz, no-wait access
2
E DataFlash Capacity: 8 Kbytes
Program/erase count: 100,000
MCU operating mode Single-chip mode.
Clock Clock generation Main clock oscillator, low on-chip oscillator, PLL frequency synthesizer, and dedicated
circuit on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Independent settings for the system clock (ICLK), peripheral module clock (PCLKA),
peripheral module clock (PCLKB), FlashIF clock (FCLK) and clock for S12AD (PCLKD)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
The multi-function timer pulse unit 3 and the general PWM timer run in synchronization
with the peripheral module clock (PCLKA): Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
The 12-bit A/D converter runs in synchronization with the clock for S12AD (PCLKD):
Up to 50 MHz
Clock frequency The frequency of the following clocks can be measured; the main clock oscillator, PCC
accuracy circuit, and low clock oscillator dedicated for the IWDT.
measurement circuit
(CAC)
Reset Pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer reset,
watchdog timer reset, deep software standby reset, and software reset
R01DS0087EJ0100 Rev.1.00 Page 2 of 76
Aug 28, 2012