Features Datasheet RX65N Group, RX651 Group R01DS0276EJ0230 Renesas MCUs Rev.2.30 Jun 20, 2019 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory (supportive of the dual bank function), 640-KB SRAM, various communications interfaces including Ethernet MAC, SD host interface (optional), SD slave interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), CMOS camera interface, Graphic-LCD controller, 2D drawing engine Features PLQP0176KB-A 24 24 mm, 0.5-mm pitch PLQP0144KA-B 20 20 mm, 0.5-mm pitch PLQP0100KB-B 14 14 mm, 0.5-mm pitch 32-bit RXv2 CPU core PLQP0064KB-C 10 10 mm, 0.5-mm pitch Max. operating frequency: 120 MHz Capable of 240 DMIPS in operation at 120 MHz Single precision 32-bit IEEE-754 floating point PTLG0177KA-A 8 8 mm, 0.5-mm pitch Two types of multiply-and-accumulation unit (between memories PTLG0145KA-A 7 7 mm, 0.5-mm pitch PTLG0100JA-A 7 7 mm, 0.65-mm pitch and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt PLBG0176GA-A 13 13mm, 0.8-mm pitch PTBG0064KB-A 4.5 4.5mm, 0.5-mm pitch CISC Harvard architecture with 5-stage pipeline Variable-length instructions: Ultra-compact code Supports the memory protection unit (MPU) Various communications interfaces JTAG and FINE (one-line) debugging interfaces Ethernet MAC (1 channel) Low-power design and architecture PHY layer (1 channel) for host/function or OTG controller Operation from a single 2.7- to 3.6-V supply (1 channel) with full-speed USB 2.0 transfer Low power consumption: A product that supports all peripheral CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up functions draws only 0.19 mA/MHz (Typ.). to 2 channels) RTC is capable of operation from a dedicated power supply. SCIg and SCIh with multiple functionalities (up to 11 channels) Four low-power modes Choose from among asynchronous mode, clock-synchronous mode, 2 On-chip code flash memory smart-card interface mode, simplified SPI, simplified I C, and extended serial mode. Supports versions with up to 2 Mbytes of ROM SCIi with 16-byte transmission and reception FIFOs (up to 2 No wait cycles at up to 50 MHz or when the ROM cache is hit, one- channels) wait state at up to 100 MHz, two-wait state at above 100 MHz 2 I C bus interface for transfer at up to 1 Mbps (up to 3 channels) User code is programmable by on-board or off-board programming. Four-wire QSPI (1 channel) in addition to RSPIc (3 channels) Programming/erasing as background operations (BGOs) Parallel data capture unit (PDC) for the CMOS camera interface A dual-bank structure allows exchanging the start-up bank. Graphic-LCD controller (GLCDC) On-chip data flash memory 2D drawing engine (DRW2D) 32 Kbytes, reprogrammable up to 100,000 times SD host interface (optional: 1 channel) with a 1- or 4-bit SD bus for Programming/erasing as background operations (BGOs) use with SD memory or SDIO SD slave interface (optional: 1 channel) with a 1- or 4-bit SD bus for On-chip SRAM, no wait states use with SD host interface 256K/640 Kbytes of SRAM (no wait states) MMCIF with 1-, 4-, or 8-bit transfer bus width 8 Kbytes of standby RAM (backup on deep software standby) External address space Data transfer Buses for full-speed data transfer (max. operating frequency of 60 DMACAa: 8 channels MHz) DTCb: 1 channel 8 CS areas EXDMAC: 2 channels 8-, 16-, or 32-bit bus space is selectable per area DMAC for the Ethernet controller: 1 channel Independent SDRAM area (128 Mbytes) Reset and supply management Up to 25 extended-function timers Power-on reset (POR) 16-bit TPUa, MTU3a Low voltage detection (LVD) with voltage settings 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 Clock functions channels) External crystal resonator or internal PLL for operation at 8 to 24 12-bit A/D converter MHz Two 12-bit units (8 channels for unit 0 21 channels for unit 1) Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz Self diagnosis, detection of analog input disconnection 120-kHz clock for the IWDTa 12-bit D/A converter: 2 channels Real-time clock Temperature sensor for measuring temperature Adjustment functions (30 seconds, leap year, and error) within the chip Real-time clock counting and binary counting modes are selectable Time capture function Encryption functions (optional) (for capturing times in response to event-signal input) AES (key lengths: 128, 192, and 256 bits) Trusted Secure IP (TSIP) Independent watchdog timer 120-kHz (1/2 LOCO frequency) clock operation Up to 136 pins for general I/O ports 5-V tolerance, open drain, input pull-up, switchable driving ability Useful functions for IEC60730 compliance Oscillation-stoppage detection, frequency measurement, CRCA, Operating temp. range IWDTa, self-diagnostic function for the A/D converter, etc. D-version: 40 C to +85C Register write protection function can protect values in important G-version: 40 C to +105C registers against overwriting. R01DS0276EJ0230 Rev.2.30 Page 1 of 246 Jun 20, 2019RX65N Group, RX651 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different packages. Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details, see Table 1.2, Code Flash Memory Capacity and Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/10) Classification Module/Function Description CPU CPU Maximum operating frequency: 120 MHz 32-bit RX CPU (RXv2) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory Code flash memory Capacity: 512 Kbytes/768 Kbytes/1 Mbyte/1.5 Mbytes/2 Mbytes 50 MHz No-wait cycle access 100 MHz 1-wait cycle access 100 MHz 2-wait cycle access Instructions hitting the ROM cache or operand = 120 MHz: No-wait access On-board programming: Four types Off-board programming (parallel programmer mode) Instructions are executable only for the program stored in the TM target area by using the Trusted Memory (TM) function and protection against data reading is realized. A dual-bank structure allows programming during reading or exchanging the start-up areas Data flash memory Capacity: 32 Kbytes Programming/erasing: 100,000 times Unique ID 16-byte unique ID for the device RAM Capacity: 256 Kbytes (Products with 1 Mbyte of code flash memory or less) RAM: 256 Kbytes Capacity: 640 Kbytes (Products with at least 1.5 Mbytes of code flash memory) RAM: 256 Kbytes Expansion RAM: 384 Kbytes 120 MHz, no-wait access Standby RAM Capacity: 8 Kbytes Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access R01DS0276EJ0230 Rev.2.30 Page 2 of 246 Jun 20, 2019