Features Datasheet RX71M Group R01DS0249EJ0110 Renesas MCUs Rev.1.10 Dec 28, 2017 240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface Features PLQP0176KB-A 24 24 mm, 0.5-mm pitch PLQP0144KA-A 20 20 mm, 0.5-mm pitch PLQP0100KB-A 14 14 mm, 0.5-mm pitch 32-bit RXv2 CPU core Max. operating frequency: 240 MHz Capable of 480 DMIPS in operation at 240 MHz PTLG0177KA-A 8 8 mm, 0.5-mm pitch Single precision 32-bit IEEE-754 floating point PTLG0145KA-A 7 7 mm, 0.5-mm pitch Two types of multiply-and-accumulation unit (between memories PTLG0100JA-A 7 7 mm, 0.65-mm pitch and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) PLBG0176GA-A 13 13mm, 0.8-mm pitch Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions: Ultra-compact code Supports the memory protection unit (MPU) Various communications interfaces JTAG and FINE (one-line) debugging interfaces IEEE 1588-compliant Ethernet MAC (for 176- and 177-pin products: 2 modules) Low-power design and architecture PHY layer for host/function or OTG controller (1) with high-speed Operation from a single 2.7- to 3.6-V supply USB 2.0 with battery charging transfer (only for 176- and 177-pin Low power consumption: A product that supports all peripheral products) functions draws only 0.2mA/MHz (Typ.). RTC is capable of operation from a dedicated power supply. PHY layer (1) for host/function or OTG controller (1) with full- Four low-power modes speed USB 2.0 transfer CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up On-chip code flash memory to 3 modules) Supports versions with up to 4 Mbytes of ROM SCIg and SCIh with multiple functionalities (up to 9) No wait states at up to 120 MHz or when the AFU is hit, one wait Choose from among asynchronous mode, clock-synchronous mode, state at above 120 MHz and when the AFU is missed 2 smart-card interface mode, simplified SPI, simplified I C, and User code is programmable by on-board or off-board programming. extended serial mode. Programming/erasing as background operations (BGOs) SCIFA with 16-byte transmission and reception FIFOs (up to 4 On-chip data flash memory interfaces) 64 Kbytes, reprogrammable up to 100,000 times 2 I C bus interface for transfer at up to 1 Mbps (up to 2 interfaces) Programming/erasing as background operations (BGOs) Four-wire QSPI (1 interface) in addition to RSPIa (2 interfaces) Parallel data capture unit (PDC) for the CMOS camera interface (not On-chip SRAM in 100-pin products) 512 Kbytes of SRAM (no wait states except in the 256 Kbytes from SD host interface (optional: 1 interface) with a 1- or 4-bit SD bus for 0004 0000h to 0007 FFFFh when ICLK is set to 120 MHz or faster) use with SD memory or SDIO 32 Kbytes of RAM with ECC (single-error correction and double MMCIF with 1-, 4-, or 8-bit transfer bus width error detection) 8 Kbytes of standby RAM (backup on deep software standby) External address space Buses for full-speed data transfer (max. operating frequency of 60 Data transfer MHz) DMAC: 8 channels 8 CS areas DTC 8-, 16-, or 32-bit bus space is selectable per area EXDMAC: 2 channels Independent SDRAM area (128 Mbytes) DMAC for the Ethernet controller: 3 channels for 176- and 177-pin products 2 channels for 100-, 144-, and 145-pin products Up to 29 extended-function timers 16-bit TPUa, MTU3a, and GPTA: input capture, output compare, Reset and supply management PWM waveform output Power-on reset (POR) 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 Low voltage detection (LVD) with voltage settings channels) Clock functions 12-bit A/D converter External crystal resonator or internal PLL for operation at 8 to 24 Two 12-bit units (8 channels for unit 0 21 channels for unit 1) MHz Self diagnosis Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 Detection of analog input disconnection MHz 120-kHz clock for the IWDTa 12-bit D/A converter: 2 channels Real-time clock On-chip operational amplifier output or direct input selectable Adjustment functions (30 seconds, leap year, and error) Temperature sensor for measuring temperature Real-time clock counting and binary counting modes are selectable within the chip Time capture function (for capturing times in response to event-signal input) Encryption (optional) AES (key lengths: 128, 192, and 256 bits) Independent watchdog timer DES (key lengths: 56 bits (DES) 3 56 bits (T-DES)) 120-kHz (1/2 LOCO frequency) clock operation SHA (SHA-1 (128), SHA-2 (224 or 256), HMAC (160, 224, or 256)) Useful functions for IEC60730 compliance Up to 127 pins for general I/O ports Oscillation-stoppage detection, frequency measurement, CRC, 5-V tolerance, open drain, input pull-up, switchable driving ability IWDTa, self-diagnostic function for the A/D converter, etc. Register write protection function can protect values in important Operating temp. range registers against overwriting. 40C to +85C R01DS0249EJ0110 Rev.1.10 Page 1 of 232 Dec 28, 2017RX71M Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/9) Classification Module/Function Description CPU CPU Maximum operating frequency: 240 MHz 32-bit RX CPU (RXv2) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory Code flash memory Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes No-wait access at up to 120 MHz, single wait access at frequencies above 120 MHz No-wait access to instructions and operands when the AFU is hit in operation at 240 MHz On-board programming: Four types Off-board programming (parallel programmer mode) The trusted memory (TM) function protects against the reading of programs from blocks 8 and 9. Data flash memory Capacity: 64 Kbytes Programming/erasing: 100,000 times RAM Capacity: 512 Kbytes 0000 0000h to 0003 FFFFh (256 Kbytes): 240 MHz No-wait access 0004 0000h to 0007 FFFFh (256 Kbytes): No-wait access at up to 120 MHz, single wait access at frequencies above 120 MHz SED (single error detection) Unique ID 12-byte length ID unique to the device RAM with ECC Capacity: 32 Kbytes (ECCRAM) Single wait access at up to 120 MHz, two wait accesses for reading and three wait accesses for writing at frequencies above 120 MHz SEC-DED (single error correction/double error detection) Standby RAM Capacity: 8 Kbytes Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access R01DS0249EJ0110 Rev.1.10 Page 2 of 232 Dec 28, 2017