R32C/111 Group Datasheet Datasheet R32C/111 Group R01DS0062EJ0130 RENESAS MCU Rev.1.30 Mar 3, 2014 1. Overview 1.1 Features The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields. The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture, multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on- 2 chip peripheral devices UART, CRC, DMAC, A/D and D/A converters, timers, I C-bus interface, and watchdog timer enables to minimize external components. The R32C/111 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin plastic molded LGA, and 100-/64-pin plastic molded LQFP packages, has a maximum of nine channels of serial interface. 1.1.1 Applications Audio, cameras, television, home appliance, printer, meter, office/industrial equipment, communication/ portable devices R01DS0062EJ0130 Rev.1.30 Page 1 of 93 Mar 3, 2014R32C/111 Group 1. Overview 1.1.2 Performance Overview Tables 1.1 to 1.4 show the performance overview of the R32C/111 Group. Table 1.1 Performance Overview for the 100-pin Package (1/2) Unit Function Explanation CPU Central R32C/100 Series CPU Core processing unit Basic instructions: 108 Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) Multiplier: 32-bit 32-bit 64-bit Multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit IEEE-754 compatible FPU: Single precision 32-bit barrel shifter Operating mode: Single-chip mode, memory expansion mode, (1) microprocessor mode (optional ) Memory Flash memory: 256 to 512 Kbytes RAM: 32 to 63 Kbytes Data flash: 4 Kbytes 2 blocks Refer to Table 1.5 for memory size of each product group (1) Voltage Low voltage Optional Detector detector Low voltage detection interrupt Clock Clock generator 4 circuits (main clock, sub clock, PLL, on-chip oscillator) Oscillation stop detector: Main clock oscillator stop/restart detection Frequency divide circuit: Divide-by-2 to divide-by-24 selectable Low power modes: Wait mode, stop mode External Bus Bus and memory Address space: 4 Gbytes (of which up to 64 Mbytes is user Expansion expansion accessible) External bus Interface: Support for wait-state insertion, 4 chip select outputs, 3V/5V interface Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16 bits) Interrupts Interrupt vectors: 261 External interrupt inputs: NMI, INT 6, key input 4 Interrupt priority levels: 7 Watchdog Timer 15 bits 1 (selectable input frequency from prescaler output) DMA DMAC 4 channels Cycle-steal transfer mode Request sources: 51 2 transfer modes: Single transfer, repeat transfer DMAC II Triggered by an interrupt request of any peripheral 3 characteristic transfer functions: Immediate data transfer, calculation result transfer, chain transfer I/O Ports Programmable 2 input-only ports I/O ports 82 CMOS I/O ports 2 N-channel open drain ports A pull-up resistor is selectable for every 4 input ports Note: 1. Contact a Renesas Electronics sales office to use the optional features. R01DS0062EJ0130 Rev.1.30 Page 2 of 93 Mar 3, 2014