Datasheet R01DS0228EJ0160 RZ/T1 Group Rev.1.60 Nov. 30, 2020 1 300 MHz/450 MHz/600 MHz, MCU with Arm Cortex -R4 and -M3* , on-chip FPU, 498/747/996 1 DMIPS, up to 1 Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT* , USB 2.0 high-speed, CAN, various communications interfaces such as an SPI multi-I/O bus controller, interface, safety 1 1 functions, encoder interfaces* , and security functions* Features On-chip 32-bit Arm Cortex-R4 processor High-speed realtime control with maximum operating frequency of 300/450/600 MHz Capable of 498/747/996 DMIPS (in operation at 300/450/600 MHz) On-chip 32-bit Arm Cortex-R4 (revision r1p4) PRBG0320GA-A 1717 mm, 0.8-mm pitch Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes Instruction cache/data cache with ECC: 8 Kbytes per cache High-speed interrupt The FPU supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at single- precision and double-precision. Harvard architecture with 8-stage pipeline PLQP0176LD-A 20 20 mm, 0.4-mm pitch Supports the memory protection unit (MPU) Arm CoreSight architecture, includes support for debugging through JTAG and SWD interfaces Various communications interfaces On-chip 32-bit Arm Cortex-M3 processor Ethernet (in products incorporating an R-IN engine) - EtherCAT slave controller: 2 ports (optional) - Ethernet MAC: 1 port (an Ethernet switch is not used) 150-MHz operating frequency or On-chip 32-bit Arm Cortex-M3 (revision r2p1) - Ethernet MAC: 1 port (an Ethernet switch to support 2 ports is RISC Harvard architecture with 3-stage pipeline used) Supports the memory protection unit (MPU) USB 2.0 high-speed host/function : 1 channel Low power consumption CAN (compliant with ISO11898-1): 2 channels (max.) Standby mode, sleep mode, and module stop function SCIFA with 16-byte transmission and reception FIFOs: 5 channels 2 I C bus interface: 2 channels for transfer at up to 400 kbps On-chip extended SRAM RSPIa: 4 channels Up to 1 Mbyte of the on-chip extended SRAM with ECC SPIBSC: Provides a single interface for multi-I/O compatible 150 MHz serial flash memory Data transfer External address space DMAC: 16 channels 2 units Buses for high-speed data transfer at 75 MHz (max.) DMAC for the Ethernet controller: 1 channel Support for up to 6 CS areas Event link controller 8-, 16-, or 32-bit bus space is selectable per area Module operations can be started by event signals rather than by Up to 33 extended-function timers interrupt handlers. 16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4 Linked operation of modules is available even while the CPU is in channels): Input capture, output compare, PWM waveform output the sleep state. 16-bit CMT (6 channels), 32-bit CMTW (2 channels) Reset and power supply voltage control Serial sound interface (1 channel) Four reset sources including a pin reset Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V interface (internal) Up to 4 modulators are connectable externally. Clock functions 12-bit A/D converters External clock/oscillator input frequency: 25 MHz 12 bits 2 units (max.) CPU clock frequency: Up to 300/450/600 MHz (8 channels for unit 0 16 channels for unit 1) Low-speed on-chip oscillator (LOCO): 240 kHz Self diagnosis Detection of analog input disconnection Independent watchdog timer Operated by a clock signal obtained by frequency-dividing the Temperature sensor for measuring temperature clock signal from the low-speed on-chip oscillator: Up to 120 kHz within the chip Safety functions General-purpose I/O ports Register write protection, input clock oscillation stop detection, 5-V tolerance, open drain, input pull-up CRC, IWDTa, and A/D self-diagnosis Multi-function pin controller An error control module is incorporated to generate a pin signal The locations of input/output functions for peripheral modules are output, interrupt, or internal reset in response to errors originating selectable from among multiple pins. in the various modules. Operating temperature range 2 Security functions (optional)* Tj = -40C to +125C Boot mode with security through encryption Tj: Junction temperature Encoder interfaces (optional) 3 2 channels* EnDat 2.2, BiSS-C, FA-CODER, A-format, and HIPERFACE 4 DSL-compliant interfaces* Frequency-divided output from an encoder Note 1. Optional Note 2. Details of these optional functions will only be disclosed after completion of a binding non-disclosure agreement. For details, contact our sales representative. Note 3. For use of two channels, use them in combination of any two protocols among EnDat2.2, BiSS-C, FA-CODER, and A-format. Note 4. BiSS is a registered trademark of iC-Haus GmbH. R01DS0228EJ0160 Rev.1.60 Page 1 of 136 Nov. 30, 2020RZ/T1 Group 1. Overview 1. Overview 1.1 Outline of Specifications This LSI circuit is a high-performance MCU equipped with the Arm Cortex -R4 processor with FPU and Cortex-M3 processor (for products incorporating an R-IN engine), and incorporating integrated peripheral functions necessary for system configuration. Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package. For details, see Table 1.2, List of Functions. Table 1.1 Outline of Specifications (1 / 7) Classification Module/Function Description CPU Central processing unit Maximum operating frequency (Cortex-R4) 320-pin FBGA: 300 MHz/450 MHz/600 MHz 176-pin HLFQFP: 450 MHz 32-bit CPU Cortex-R4 designed by Arm (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC) Data cache: 8 Kbytes (with ECC) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC) BTCM: 32 Kbytes (with ECC) Instruction set: Arm v7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Central processing unit Operating frequency: 150 MHz (Cortex-M3) 32-bit CPU Cortex-M3 designed by Arm (core revision r2p1) (for products Address space: 4 Gbytes incorporating an R-IN Instruction set: Arm v7-M architecture, so support includes Thumb and Thumb-2 engine) Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) FPU Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and (Cortex-R4) square-root operations at single- and double-precision. Registers 32-bit single-word registers: 32 bits 32 (can be used as 16 double-word registers: 64 bits 16) Memory On-chip extended Capacity: Up to 1 Mbyte SRAM with ECC Operating frequency: 150 MHz SEC-DED (single error correction/double error detection) Operating modes The operating mode can be selected from the following three boot modes SPI boot mode (for booting up from serial flash memory) 16-bit bus boot mode (NOR Flash) 32-bit bus boot mode (NOR Flash) Clock Clock generation circuit The input clock can be selected from an external clock or external resonator. Detection of input clock oscillation stopping The following clocks are generated. CPU clock: 300/450/600 MHz (max.) System clock: 150 MHz (fixed) High-speed peripheral module clock: 150 MHz (fixed) Low-speed peripheral module clock: 75 MHz (fixed) ADCCLK in the 12-bit A/D converter (S12ADCa): 60 MHz (max.) External bus clock: 75 MHz (max.) Low-speed on-chip oscillator: 240 kHz (fixed) Reset RES pin reset, error control module (ECM) reset, software reset R01DS0228EJ0160 Rev.1.60 Page 2 of 136 Nov. 30, 2020