Datasheet R01DS0273EJ0300 RX130 Group Rev.3.00 Renesas MCUs Aug 09, 2018 32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 512-KB flash memory, up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply Features 32-bit RX CPU core Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz PLQP0100KB-B 14 14mm, 0.5mm pitch Accumulator handles 64-bit results (for a single instruction) from PLQP0080KB-B 12 12mm, 0.5mm pitch PLQP0064GA-A 14 14mm, 0.8mm pitch 32-bit 32-bit operations PLQP0064KB-C 10 10mm, 0.5mm pitch Multiplication and division unit handles 32-bit 32-bit operations PLQP0048KB-B 7 7mm, 0.5mm pitch (multiplication instructions take one CPU clock cycle) Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions, ultra-compact code On-chip debugging circuit Low power design and architecture Operation from a single 1.8-V to 5.5-V supply PWQN0048KB-A 7 7mm, 0.5mm pitch Three low power consumption modes Low power timer (LPT) that operates during the software standby state Supply current High-speed operating mode: 96 A/MHz Supply current in software standby mode: 0.37 A MPC Recovery time from software standby mode: 4.8 s Input/output functions selectable from multiple pins On-chip flash memory for code, no wait states Up to 6 communication functions SCI with many useful functions (up to 4 channels) 64 K/128 K/256 K/383 K/512 Kbytes Operation at 32 MHz, read cycle of 31.25 ns Asynchronous mode (Fine adjustable baud rate: 0 to 255/255), clock synchronous mode, smart card interface mode No wait states for reading at full CPU speed 2 Programmable at 1.8 V I C bus interface: Transfer at up to 400 kbps, capable of SMBus For instructions and operands operation (one channel) RSPI (one channel): Transfer at up to 16 Mbps On-chip data flash memory Remote control signal reception 8 Kbytes (1,000,000 program/erase cycles (typ.)) Two units integrated BGO (Background Operation) Four pattern waveform matching supported On-chip SRAM, no wait states Up to 12 extended-function timersMPC 10 K/16 K/32 K/48 Kbytes size capacities 16-bit MTU: input capture, output compare, complementary PWM output, phase counting mode (six channels) DTC 8-bit TMR (four channels) Four transfer modes 16-bit compare-match timers (two channels) Transfer can be set for each interrupt source. 12-bit A/D converter ELC Capable of conversion within 1.4 s Module operation can be initiated by event signals without using 17 channels interrupts. Sampling time can be set for each channel Linked operation between modules is possible while the CPU is sleeping. Conversion results compare features Self-diagnostic function and analog input disconnection detection Reset and supply management assistance function Eight types of reset, including the power-on reset (POR) Double trigger (data duplication) function for motor control Low voltage detection (LVD) with voltage settings D/A converter Clock functions Two channels External clock input frequency: Up to 20 MHz Capacitive touch sensing unit Main clock oscillator frequency: 1 to 20 MHz Self-capacitance method: A single pin configures a single key, Sub clock oscillator frequency: 32.768 kHz supporting up to 36 keys PLL circuit input: 4 MHz to 8 MHz Mutual capacitance method: Matrix configuration with 36pins, supporting Low-speed on-chip oscillator: 4 MHz up to 324 keys High-speed on-chip oscillator: 32 MHz 1 % IWDT-dedicated on-chip oscillator: 15 kHz Comparator B Generate a 32.768 kHz clock for the real-time clock Two channels On-chip clock frequency accuracy measurement circuit (CAC) General I/O ports Realtime clock 5-V tolerant, open drain, input pull-up, switching of driving capacity Adjustment functions (30 seconds, leap year, and error) Calendar count mode or binary count mode selectable Temperature sensor Independent watchdog timer Unique ID 15-kHz on-chip oscillator produces a dedicated clock signal to drive 32-byte ID code for the MCU IWDT operation. Operating temperature range Useful functions for IEC60730 compliance 40 to +85C Self-diagnostic and disconnection-detection assistance functions for 40 to +105C the A/D converter, clock frequency accuracy measurement circuit, independent watchdog timer, RAM test assistance functions using the Applications DOC, etc. General industrial and consumer equipment R01DS0273EJ0300 Rev.3.00 Page 1 of 134 Aug 09, 2018RX130 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages in the RX130 Group. Table 1.1 Outline of Specifications (1/3) Classification Module/Function Description CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit registers Basic instructions: 73 (variable-length instruction format) DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit 32-bit 64-bit On-chip divider: 32-bit 32-bit 32 bits Barrel shifter: 32 bits Memory ROM Capacity: 64 K/128 K/256 K/383 K/512 Kbytes No-wait memory access Programming/erasing method: Serial programming (asynchronous serial communication), self-programming RAM Capacity: 10 K/16 K/32 K/48 Kbytes No-wait memory access E2 DataFlash Capacity: 8 Kbytes Number of erase/write cycles: 1,000,000 (typ) MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator Oscillation stop detection: Available Clock frequency accuracy measurement circuit (CAC) Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 32 MHz (at max.) Peripheral modules run in synchronization with the PCLKB: 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1,2,4,8,16,32,64) Resets RES pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt (LVDAb) is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels Low power Low power consumption Module stop function consumption functions Three low power consumption modes Sleep mode, deep sleep mode, and software standby mode Function for lower operating Operating power control modes power consumption High-speed operating mode, middle-speed operating mode, and low-speed operating mode Interrupt Interrupt controller (ICUb) Interrupt vectors: 115 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins) Non-maskable interrupts: 5 (The NMI pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt) 16 levels specifiable for the order of priority R01DS0273EJ0300 Rev.3.00 Page 2 of 134 Aug 09, 2018