X5323, X5325 (Replaces X25323, X25325) Data Sheet June 30, 2008 FN8131.2 CPU Supervisor with 32kBit SPI EEPROM Features These devices combine four popular functions, Power-on Selectable watchdog timer Reset Control, Watchdog Timer, Supply Voltage Supervision, Low V detection and reset assertion CC and Block Lock Protect Serial EEPROM Memory in one - Five standard reset threshold voltages package. This combination lowers system cost, reduces - Re-program low V reset threshold voltage using CC board space requirements, and increases reliability. special programming sequence Applying power to the device activates the power-on reset - Reset signal valid to V = 1V CC circuit which holds RESET/RESET active for a period of Determine watchdog or low voltage reset with a volatile time. This allows the power supply and oscillator to stabilize flag bit before the processor can execute code. Long battery life with low power consumption The Watchdog Timer provides an independent protection - <50A max standby current, watchdog on mechanism for microcontrollers. When the microcontroller - <1A max standby current, watchdog off fails to restart a timer within a selectable time out interval, - <400A max active current during read the device activates the RESET/RESET signal. The user 32kbits of EEPROM selects the interval from three preset values. Once selected, Built-in inadvertent write protection the interval does not change, even after cycling the power. - Power-up/power-down protection circuitry The devices low V detection circuitry protects the users CC - Protect 0, 1/4, 1/2 or all of EEPROM array with Block system from low voltage conditions, resetting the system Lock protection when V falls below the minimum V trip point. CC CC - In circuit programmable ROM mode RESET/RESET is asserted until V returns to proper CC 2MHz SPI interface modes (0,0 and 1,1) operating level and stabilizes. Five industry standard V TRIP Minimize EEPROM programming time thresholds are available, however, Intersils unique circuits - 32-byte page write mode allow the threshold to be reprogrammed to meet custom - Self-timed write cycle requirements or to fine-tune the threshold for applications - 5ms write cycle time (typical) requiring higher precision. 2.7V to 5.5V and 4.5V to 5.5V power supply operation Available packages - 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP Pb-free (RoHS compliant) Block Diagram WATCHDOG TRANSITION WATCHDOG DETECTOR TIMER RESET WP PROTECT LOGIC RESET/RESET SI DATA STATUS REGISTER SO REGISTER X5323 = RESET RESET AND COMMAND X5325 = RESET SCK DECODE AND 8kBITS WATCHDOG CONTROL TIMEBASE CS/WDI LOGIC 8kBITS V THRESHOLD CC 16kBITS RESET LOGIC POWER-ON AND LOW VOLTAGE V + CC RESET - GENERATION V TRIP CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EEPROM ARRAYX5323, X5325 Ordering Information PART NUMBER PART NUMBER RESET PART RESET PART V RANGE TEMP CC (ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING (V) V RANGE RANGE (C) PACKAGE TRIP X5323P-4.5A X5323P AL X5325P-4.5A X5325P AL 4.5 to 5.5 4.5 to 4.75 0 to +70 8 Ld PDIP X5323PZ-4.5A (Note) X5323P ZAL X5325PZ-4.5A X5325P ZAL 0 to +70 8 Ld PDIP** (Pb-free) X5323PI-4.5A X5323P AM X5325PI-4.5A X5325P AM -40 to +85 8 Ld PDIP X5323PIZ-4.5A (Note) X5323P ZAM X5325PIZ-4.5A X5325P ZAM -40 to +85 8 Ld PDIP** (Pb-free) X5323S8-4.5A X5323 AL X5325S8-4.5A X5325 AL 0 to +70 8 Ld SOIC X5323S8Z-4.5A (Note) X5323 ZAL X5325S8Z-4.5A (Note) X5325 ZAL 0 to +70 8 Ld SOIC (Pb-free) X5323S8I-4.5A* X5323 AM X5325S8I-4.5A X5325 AM -40 to +85 8 Ld SOIC X5323S8IZ-4.5A* X5323 ZAM X5325S8IZ-4.5A X5325 ZAM -40 to +85 8 Ld SOIC (Pb-free) (Note) (Note) X5323V14-4.5A X5323 VAL X5325V14-4.5A X5325 VAL 0 to +70 14 Ld TSSOP X5323V14Z-4.5A X5323 VZAL X5325V14Z-4.5A X5325 VZAL 0 to +70 14 Ld TSSOP (Note) (Note) (Pb-free) X5323V14I-4.5A X5323 VAM X5325V14I-4.5A X5325 VAM -40 to +85 14 Ld TSSOP X5323V14IZ-4.5A X5323 VZAM X5325V14IZ-4.5A X5325 VZAM -40 to +85 14 Ld TSSOP (Note) (Note) (Pb-free) X5323P X5323P X5325P X5325P 4.5 to 5.5 4.25 to 4.5 0 to +70 8 Ld PDIP X5323PZ (Note) X5323P Z X5325PZ X5325P Z 0 to +70 8 Ld PDIP** (Pb-free) X5323PI X5323P I X5325PI X5325P I -40 to +85 8 Ld PDIP X5323PIZ (Note) X5323P ZI X5325PIZ X5325P ZI -40 to +85 8 Ld PDIP** (Pb-free) X5323S8* X5323 X5325S8* X5325 0 to +70 8 Ld SOIC X5323S8Z* (Note) X5323 Z X5325S8Z* (Note) X5325 Z 0 to +70 8 Ld SOIC (Pb-free) X5323S8I* X5323 I X5325S8I* X5325 I -40 to +85 8 Ld SOIC X5323S8IZ* (Note) X5323 ZI X5325S8IZ* (Note) X5325 ZI -40 to +85 8 Ld SOIC (Pb-free) X5323V14* X5323 V X5325V14* X5325 V 0 to +70 14 Ld TSSOP X5323V14Z* (Note) X5323 VZ X5325V14Z* (Note) X5325 VZ 0 to +70 14 Ld TSSOP (Pb-free) X5323V14I* X5323 VI X5325V14I* X5325 VI -40 to +85 14 Ld TSSOP X5323V14IZ* (Note) X5323 VZI X5325V14IZ* (Note) X5325 VZI -40 to +85 14 Ld TSSOP (Pb-free) X5323P-2.7A X5323P AN X5325P-2.7A X5325P AN 2.7 to 5.5 2.85 to 3.0 0 to +70 8 Ld PDIP X5323PZ-2.7A (Note) X5323P ZAN X5325PZ-2.7A X5325P ZAN 0 to +70 8 Ld PDIP** (Pb-free) X5323PI-2.7A X5323P AP X5325PI-2.7A X5325P AP -40 to +85 8 Ld PDIP X5323PIZ-2.7A (Note) X5323P ZAP X5325PIZ-2.7A X5325P ZAP -40 to +85 8 Ld PDIP** (Pb-free) X5323S8-2.7A* X5323 AN X5325S8-2.7A X5325 AN 0 to +70 8 Ld SOIC X5323S8Z-2.7A* X5323 ZAN X5325S8Z-2.7A (Note) X5325 ZAN 0 to +70 8 Ld SOIC (Pb-free) (Note) X5323S8I-2.7A* X5323 AP X5325S8I-2.7A X5325 AP -40 to +85 8 Ld SOIC X5323S8IZ-2.7A* X5323 ZAP X5325S8IZ-2.7A X5325 ZAP -40 to +85 8 Ld SOIC (Pb-free) (Note) (Note) FN8131.2 2 June 30, 2008