X80200, X80201, X80202, X80203, X80204 Data Sheet January 21, 2005 FN8154.0 Power Supply Sequencer with Power-up Features System Monitoring Sequence three voltage supplies independently The X80200 power sequencer provides a flexible approach - Core and Logic I/O VCC power sequencer for processor for handling difficult system power-up conditions. The supplies X80200 includes control of up to three voltage supplies and - Power up and power down control can be cascaded to control additional supplies. The device - Voltage monitors have undervoltage lockout contains independent undervoltage lockout for each - Internal charge pump drives external N-channel FET controlled voltage. switches - Cascadable to sequence more than 3 supplies The three voltage control circuits allow sequencing for - Time based or voltage based sequencing primary, core, and I/O voltages. The core and I/O supplies are linked together with a comparator or a timer allowing a Status register bits monitor gate output status tight coupling between these two supplies. The sequencing SMBus compatible Interface may be either voltage based or time based. Slave address identification for up to 8 power sequencers The X80200 contains separate charge pumps to control (24 supplies) on the same bus external N-channel power FETs for each of the supplies. The charge pumps provide the high gate control voltage Surface mount 20-pin TSSOP Package necessary for efficient operation of the FET switches. Applications The X80200 turns on the primary voltage to the system Distributed Power Supply Designs when the voltage source is steady. This primary FET switch turn-on can be delayed with an external RC circuit. For the Multi-voltage systems secondary voltage sources, the device has a built-in core- Multiprocessor systems up-first and core-down-last sequencing logic which is ideal for high performance processors, DSPs and ASICs. Embedded Processor Applications The serial bus can be used to monitor the status or turn off Digital Signal Processors, FPGAs, ASICs, Memory Controllers each of the external power switches. The X80200 has 3 slave address bits that allow up to 8 devices to be connected N + 1 Redundant Power Supplies to the same bus. Support for SSI Server System Infrastructure Specifications Pinout -48V Hotswap Power Backplane/Distribution 20 LD TSSOP TOP VIEW Card Insertion Detection and Power SETV 1 20 VDDL Power Sequencing DC-DC Supplies REF 19 2 VDDM Databus Power Interfacing A0 3 18 VDDH Custom Industrial Power Backplanes GND 17 4 VFB A1 5 16 DNC Other: ATE, Data Acquisition, Mass Storage, Servers, Data com, Wireless Basestations A2 GATE M 6 15 NC 7 14 GATE H Ordering Information 8 SDA 13 GATE L 9 12 PART NUMBER UVLO UVLO UVLO PACKAGE SCL ENS H M L 10 READY 11 GATEH EN X80200V20I 4.5 3.0 0.9 TSSOP X80201V20I 4.5 2.25 0.9 TSSOP X80202V20I 3.0 2.25 1.7 TSSOP X80203V20I 3.0 2.25 0.9 TSSOP X80204V20I 3.0 0.9 0.9 TSSOP CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 321-724-7143 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.X80200, X80201, X80202, X80203, X80204 Functional Diagram VDDH VFB DNC GATE M GATE H 18 17 16 15 14 CHARGE 13 GATE L PUMP M UVLO H OSC CHARGE PUMP H VDDM 19 UVLO M CHARGE PUMP L VDDL 20 UVLO 12 ENS L SETV 1 + CORE-UP-FIRST 11 GATEH EN CORE-DOWN-LAST REF 2 10 READY 2-WIRE STATUS REGISTER A0 3 INTERFACE REMOTE SHUTDOWN REGISTER 9 SCL 45 6 7 8 GND A1 A2 NC SDA Pin Descriptions PIN NAME DESCRIPTION 1 SETV Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL. If unused connect to ground. 2 REF Reference voltage. This pin is used for voltage based sequencing. The voltage on this pin is compared to the voltage on the VFB pin and provides the threshold for turn on of the GATE M output. Either a voltage source or external resistor divider can be used to provide the reference. If time based sequencing is used this pin should be tied to VDDH. 3 A0 Slave address pin assignment. It has an Internal pull down resistor. (>10M typical) 4 GND Voltage Ground. 5 A1 Slave address pin assignment. It has an Internal pull down resistor. (>10M typical) 6 A2 Slave Address pin assignment. It has an Internal pull down resistor. (>10M typical) 7 NC No internal connections. 8 SDA Serial bus data input/output pin. 9 SCL Serial bus clock input pin. 10 READY READY Output Pin: This open-drain output pin goes LOW while VDDH is below UVLO and remains LOW for t after H PURST VDDH goes above UVLO . READY goes HIGH after t . H PURST 11 GATEH EN GATE H Enable. When this pin is HIGH and VDDH > UVLO the charge pump of the GATE H pin turns on and the output H drives HIGH. When this pin is LOW, the charge pump is disabled and the GATE H output is LOW. An external RC time delay can be connected between the enable signal and this pin to delay the GATE H turn on. 12 ENS Enable Sequence. This pin is used for time-based power sequencing of supplies VDDM and VDDL. If unused, connect to ground. 13 GATE L GATE L Output: This output is connected to the gate of an (external) Power Switch L. The GATE L pin is driven HIGH when charge pump L is enabled and pulled LOW when the charge pump is disabled. 14 GATE H GATE H Output: This output is connected to the gate of a (external) Power Switch H. The GATE H pin driven HIGH when charge pump H is enabled and pulled LOW when the charge pump is disabled. 15 GATE M GATE M Output: This output is connected to the gate of a (external) Power Switch M. The GATE M pin driven HIGH when charge pump M is enabled and pulled LOW when the charge pump is disabled. 16 DNC Do not connect (must be left floating). 17 VFB Voltage Feedback Pin. This input pin is used with voltage based power sequencing to monitor the level of a previously turned- on supply. If unused, connect to ground. 18 VDDH Primary supply voltage (typically 5V). 19 VDDM Monitored Supply Voltage M input. 20 VDDL Monitored Supply Voltage L input. FN8154.0 2 SEQUENCE DELAY LOGIC