XLL726156.250000I Renesas

XL Family of Low Phase Noise XL Quartz-based PLL Oscillators Datasheet Description Features Output types: LVDS, LVPECL, LVCMOS The Renesas XL devices (XO and VCXO options) are ultra-precision crystal oscillators with 750 to 890fs typical phase Phase jitter (12kHz to 20MHz): 750fs to 890fs typical jitter over 12kHz to 20MHz bandwidth. Available in a wide Supply voltage: 2.5V or 3.3V frequency range from 0.750MHz to 1350MHz, the XL series Package options: crystal oscillators utilize a family of proprietary ASICs, with a key 3.2 2.5 1.0 mm (not available for VCXO) focus on noise reduction technologies. 5.0 3.2 1.2 mm The 3rd order Delta Sigma Modulator reduces noise to the levels 7.0 5.0 1.3 mm that are comparable to traditional Bulk Quartz and SAW oscillators. With short lead-time, low cost, low noise, wide Operating temperature: -20C to +70C frequency range, excellent ambient performance, the XL devices Frequency stability options: 20, 25, 50, or 100 ppm are an excellent choice over the conventional technologies. The (XO only) XL (XO option) devices have stabilities as tight as 20ppm and 50ppm APR (VCXO only) the XL (VCXO option) devices have 50ppm APR. Either option Operating temperature: -40C to +85C provides extremely quick delivery for both standard and custom Frequency stability options: 25, 50, or 100 ppm frequencies. (XO only) 50ppm APR (VCXO only) Pin Assignments Operating temperature: -40C to +105C (XO only) (XO Option) Frequency stability options: 50 or 100 ppm kV of 85ppm/volt typical from 0.5VDC to VDD (VCXO only) NOTE: To minimize power supply line noise, a 0.01F bypass capacitor should be placed between V (Pin 6) and GND (Pin 3). Better than 10% linearity for Vc range DD 6 5 4 12 3 (VCXO Option) NOTE: To minimize power supply line noise, a 0.01F bypass capacitor should be placed between V (Pin 6) and GND (Pin 3). DD 6 5 4 12 3 2021 Renesas Electronics Corporation 1 January 19, 2021 E/D / NC VDD Vc VDD NC / E/D E/D OUT2 OUT2 GND OUT GND OUTXL Datasheet Pin Descriptions Table 1. XO Pin Description Table 2. VCXO Pin Description Number Name Description Number Name Description a b 1 E/D Enable/Disable 1 Vc Voltage control NC a b No connect 2 E/D Enable/Disable 2 NC No connect 3 GND Connect to ground a b E/D Enable/Disable 4 OUT Output 3 GND Connect to ground 5 OUT2 Complementary output (NC LVCMOS) 4 OUT Output 6 V Supply voltage DD c 5 OUT2 Complementary output a Pulled high internally. 6 V Supply voltage DD b Low = output disabled. See Ordering Information (VCXO) for more details. a Pulled high internally. b Low = output disabled. c Do not connect for LVCMOS. For XLVCMOS, both OUT and OUT2 are ON and in opposite phase. See Ordering Information (XO) for more details. 2021 Renesas Electronics Corporation 2 January 19, 2021