Datasheet R01DS0190EJ0130 RX111 Group Rev.1.30 Renesas MCUs May 31, 2016 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory, USB 2.0 full-speed host/function/OTG, up to 6 comms channels, 12-bit A/D, 8-bit D/A, RTC Features 32-bit RX CPU core 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz PLQP0064KB-A 10 10 mm, 0.5 mm pitch Accumulator handles 64-bit results (for a single PLQP0064GA-A 14 14 mm, 0.8 mm pitch instruction) from 32-bit 32-bit operations PLQP0048KB-A 7 7 mm, 0.5 mm pitch Multiplication and division unit handles 32-bit 32-bit operations (multiplication instructions take one CPU clock cycle) PWQN0048KB-A 7 7 mm, 0.50 mm pitch Fast interrupt PWQN0040KC-A 6 6 mm, 0.50 mm pitch CISC Harvard architecture with five-stage pipeline Variable-length instruction format, ultra-compact code On-chip debugging circuit PWLG0064KA-A 5 5 mm, 0.5 mm pitch Low power consumption functions PWLG0036KA-A 4 4 mm, 0.5 mm pitch Operation from a single 1.8 to 3.6 V supply Three low power consumption modes Supply current Independent watchdog timer (IWDT) High-speed operating mode: 0.11 mA/MHz 15-kHz on-chip oscillator produces a dedicated clock Software standby mode: 0.44 A signal to drive IWDT operation. Recovery time from software standby mode: 4.8 s On-chip functions for IEC 60730 compliance On-chip flash memory for code, no wait states Clock frequency accuracy measurement circuit, IWDT, Operation at 32 MHz, read cycle of 31.25 ns functions to assist in RAM testing, etc. No wait states for reading at full CPU speed Up to six channels for communication 16 to 512 Kbyte capacities USB: USB 2.0 host (32 Kbyte or more ROM)/function/ Programmable at 1.8 V On-The-Go (OTG) (one channel), full-speed = 12 Mbps, For instructions and operands low-speed = 1.5 Mbps, isochronous transfer, and BC On-chip data flash memory (Battery Charger) supported 8 Kbytes SCI: Asynchronous mode, clock synchronous mode, 1,000,000 Erase/Write cycles (typ.) smart card interface (up to three channels) 2 BGO (Background Operation) I C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (one channel) On-chip SRAM, no wait states RSPI: Up to 16 Mbps (one channel) 8 to 64 Kbyte capacities Up to 8 extended-function timers Data transfer controller (DTC) 16-bit MTU: Input capture/output compare, Four transfer modes complementary PWM output, phase counting mode Transfer can be set for each interrupt source. (six channels) Event link controller (ELC) 16-bit CMT (two channels) Module operation can be initiated by event signals without 12-bit A/D converter going through interrupts. Up to 14 channels Link operation between modules is possible while the 1.0 s minimum conversion speed CPU is sleeping. Double trigger (data duplication) function for motor Reset and power supply voltage management control Six types including Power-On Reset (POR) 8-bit D/A converter Low voltage detection (LVD) with voltage settings Two channels (for 64 pins only) Clock functions Temperature sensor External clock input frequency: Up to 20 MHz Main clock oscillator frequency: 1 to 20 MHz General I/O ports Sub-clock oscillator frequency: 32.768 kHz 5-V tolerant, open drain, input pull-up PLL circuit input: 4 to 8 MHz Multi-function pin controller (MPC) Low-speed on-chip oscillator: 4 MHz Multiple I/O pins can be selected for peripheral functions. High-speed on-chip oscillator: 32 MHz1% ( 20 to 85C) Unique ID IWDT-dedicated on-chip oscillator: 15 kHz Generate a dedicated 32.768-kHz clock for the RTC 32-byte ID code for the MCU On-chip clock frequency accuracy measurement circuit Operating temperature range (CAC) 40 to 85C Realtime clock (RTC) 40 to 105C 30-second, leap year, and error adjustment functions Calendar count mode or binary count mode selectable Capable of initiating exit from software standby mode R01DS0190EJ0130 Rev.1.30 Page 1 of 127 May 31, 2016RX111 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/3) Classification Module/Function Description CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit 32-bit 64-bit On-chip divider: 32-bit 32-bit 32 bits Barrel shifter: 32 bits Memory ROM Capacity: 16 K /32 K /64 K /96 K /128 K /256 K /384 K /512 Kbytes 32 MHz, no-wait memory access Programming/erasing method: Serial programming (asynchronous serial communication/USB communication), self-programming RAM Capacity: 8 K /10 K /16 K /32 K /64 Kbytes 32 MHz, no-wait memory access E2 DataFlash Capacity: 8 Kbytes Number of erase/write cycles: 1,000,000 (typ) MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator Oscillation stop detection: Available Clock frequency accuracy measurement circuit (CAC) Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 32 MHz (at max.) Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32, 64). Resets RES pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt (LVDAa) is generated. Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels Low power Low power consumption Module stop function consumption functions Three low power consumption modes Sleep mode, deep sleep mode, and software standby mode Function for lower operating Operating power control modes power consumption High-speed operating mode, middle-speed operating mode, and low-speed operating mode Interrupt Interrupt controller (ICUb) Interrupt vectors: 82 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins) Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt) 16 levels specifiable for the order of priority R01DS0190EJ0130 Rev.1.30 Page 2 of 127 May 31, 2016