ZL6105ALAF Renesas

DATASHEET ZL6105 FN6906 Rev 6.0 Digital DC/DC Controller with Drivers and Auto Compensation Jun 22, 2021 The ZL6105 is a digital power controller with integrated Features MOSFET drivers. Auto compensation eliminates the need for manual compensation design work. Adaptive performance Power Conversion optimization algorithms improve power conversion efficiency. Efficient Synchronous Buck Controller Zilker Labs Digital-DC technology enables a blend of power conversion performance and power management features. Auto Compensating PID Filter The ZL6105 is designed to be a flexible building block for DC Adaptive Light Load Efficiency Optimization power and can be easily adapted to designs ranging from a 3V to 14V Input Range single-phase power supply operating from a 3.3V to a 0.54V to 5.5V Output Range (with margin) multiphase current sharing supply operating from a 12V input. The ZL6105 eliminates the need for complicated power supply 1% Output Voltage Accuracy managers as well as numerous external discrete components. Internal 3A MOSFET Drivers 2 The ZL6105 uses the I C/SMBus with PMBus protocol for Fast Load Transient Response communication with a host controller and the Digital-DC bus Current Sharing and Phase Interleaving for communication between Zilker Labs devices. Snapshot Parameter Capture The ZL6105 is pin for pin compatible with the ZL2008. The Pb-Free (RoHs Compliant) POLA V table and compensation table have been removed. OUT A new single resistor V table and the Auto Compensation OUT Power Management feature have been added. Digital Soft-start/stop Applications Power-Good/Enable Servers/Storage Equipment Voltage Tracking, Sequencing and Margining Telecom/Datacom Equipment Voltage, Current and Temperature Monitoring Power Supply Modules 2 I C/SMBus Interface, PMBus Compatible Output Voltage and Current Protection Internal Non-volatile Memory (NVM) 100 EN PG PH EN FC ILIM CFG UVLO V25 VR VDD V = 3.3V OUT V = 1.5V 95 OUT 90 V SS LDO 85 VTRK POWER MGN MANAGEMENT BST SYNC 80 GH DDC DRIVER 75 SW GL 70 NON- VSEN+ PWM VOLATILE VSEN- CONTROLLER 65 MEMORY CURRENT ISENA SENSE ISENB 60 SCL V = 12V IN MONITOR TEMP 2 55 SDA I C f = 400kHz SENSOR SW ADC SALRT 3 Circuit of Figure 4 50 0 4 10 14 16 18 20 2 6812 SA XTEMP PGND SGND DGND Load Current (A) FIGURE 1. BLOCK DIAGRAM FIGURE 2. EFFICIENCY vs LOAD CURRENT FN6906 Rev 6.0 Page 1 of 35 Jun 22, 2021 2011 Renesas Electronics Efficiency (%)ZL6105 Table of Contents Typical Application Circuit 3 Pin Descriptions . 5 Absolute Maximum Ratings 7 Thermal Information . 7 Recommended Operating Conditions 7 Electrical Specifications . 7 ZL6105 Overview . 10 Digital-DC Architecture . 10 Power Conversion Overview . 10 Power Management Overview . 11 Multi-mode Pins . 11 Power Conversion Functional Description . 12 Internal Bias Regulators and Input Supply Connections . 12 High-side Driver Boost Circuit 12 Output Voltage Selection . 12 Single Resistor Output Voltage Setting Mode 13 SMBus Mode . 13 Start-up Procedure . 13 Soft-Start Delay and Ramp Times 14 Power-Good 15 Switching Frequency and PLL . 15 Power Train Component Selection . 16 Current Limit Threshold Selection 19 Loop Compensation . 20 Non-linear Response (NLR) Settings 22 Efficiency Optimized Driver Dead-time Control . 22 Adaptive Diode Emulation 22 Power Management Functional Description 22 Input Undervoltage Lockout . 22 Output Overvoltage Protection . 23 Output Pre-Bias Protection 23 Output Overcurrent Protection . 24 Thermal Overload Protection 24 Voltage Tracking 24 Voltage Margining . 25 I2C/SMBus Communications 25 I2C/SMBus Device Address Selection . 26 Digital-DC Bus 26 Phase Spreading 27 Output Sequencing 28 Fault Spreading . 28 Temperature Monitoring Using the XTEMP Pin . 28 Active Current Sharing . 28 Phase Adding/Dropping 31 Monitoring via I2C/SMBus 31 Snapshot Parameter Capture . 31 Non-Volatile Memory and Device Security Features . 32 License Information 32 Revision History 33 Package Outline Drawing 35 FN6906 Rev 6.0 Page 2 of 35 Jun 22, 2021