Datasheet 4.2V to 18V, 2A 1ch Synchronous Buck Converter integrated FET BD1482EFJ General Description Key Specifications The BD1482EFJ is a synchronous step-down Input voltage range: 4.2V to 18V switching regulator that integrates 2 low ON-resistance Output voltage range: 0.923V to (Vin0.7)V N-channel MOSFETs. It achieves 2A continuous Output current: 2.0A (Max.) output current over a wide input supply range. Current Switching Frequency 380kHz(Typ.) mode operation provides fast transient response and Hi-side FET On-resistance: 0.15(Typ.) easy phase compensation. Lo-side FET On-resistance: 0.13(Typ.) Standby current: 15 A (Typ.) Features Operating temperature range: -40 to +85 Low ESR Output Ceramic Capacitors are Available Package (Typ.) (Typ.) (Max.) Low Standby Current during Shutdown Mode HTSOP-J8 4.90mm x 6.00mm x 1.00mm 380 kHz Fixed Operating Frequency Feedback voltage 0.923V 1.5%(Ta=25), 0.923V 2.0%(Ta=-25 to 85) Protection Circuits Under Voltage Lockout Protection Thermal Shutdown Over Current Protection Applications Distributed Power System Pre-Regulator for Linear Regulator HTSOP-J8 Typical Application Circuit C PC 3300pF R PC R DW 7.5k 15k C SS 0.1F R UP 39k Thermal Pad (to be shorted to GND) L VIN 12V VOUT 3.3V 10H C CO1 C VC1 10F 20F R BS protect from VIN-BST short destruction. Fig.1 Typical Application Circuit Product structureSilicon monolithic integrated circuit This product is not designed protection against radioactive rays. www.rohm.com TSZ02201-0333AD100130-1-2 2012 ROHM Co., Ltd. All rights reserved. 1/17 06.Aug.2012 Rev.001 TSZ2211114001 Not Recommended for New Designs BST SS R BS 22 VIN EN C BS 0.1F SW COMP GND FB Datasheet BD1482EFJ Pin Configuration Block Diagram (TOP VIEW) SS EN COMP FB BST VIN SW GND Fig.2 Pin Configuration Fig.3 Block Diagram Pin Description Pin No. Pin name Function 1 BST High-Side Gate Drive Boost Input 2 VIN Power Input 3 SW Power Switching Output 4 GND Ground 5 FB Feed Back Input 6 COMP Compensation Node 7 EN Enable Input 8 SS Soft Start Control Input Block Operation VREG A block to generate constant-voltage for DC/DC boosting. VREF A block that generates internal reference voltage of 5.1 V (Typ.). TSD/UVLO TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block. The TSD circuit shuts down IC at high temperature. The UVLO circuit shuts down the IC when the VIN is Low Voltage. Error amp block (ERR) This is the circuit to compare the reference voltage and the feedback voltage of output voltage. The COMP pin voltage resulting from this comparison determines the switching duty. At the time of startup, since the soft start is operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage. Oscillator block (OSC) This block generates the oscillating frequency. SLOPE block This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to the PWM comparator. PWM block The COMP pin voltage output by the error amp is compared to the SLOPE block s triangular waveform to determine the switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not become 100%. DRV block A DC/DC driver block. A signal from the PWM is input to drive the power FETs. OCP block OCP (Over Current Protection) block. The current which flowed into FET is detected and OCP starts at 3.5A (min). After OCP, switching is turned off and SS capacitor is discharged. OCP is not latch type but auto restart. Soft start circuit Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the output voltage overshoot or the rush current. www.rohm.com TSZ02201-0333AD100130-1-2 2012 ROHM Co., Ltd. All rights reserved. 2/17 06.Aug.2012 Rev.001 TSZ2211115001 Not Recommended for New Designs