Datasheet Built-in OVP Micro USB Switch TM with USB2.0, MHL and Audio BD91411GW General Description Key Specifications BD91411GW is USB connector interface IC. OVP switch ON resistance: 120m(Typ.) It is possible to use it for the application for the mobile Over Current Protection(OCP): 2.0A(Min.) device such as smart phones and mobile phones. Regulator output voltage: 3.3V or 4.9V MHL/USB switch ON resistance: 5(Typ.) Features MHL/USB switch ON capacitance: 6pF(Typ.) Complete solution for mini/micro USB connect VBAT standby current: 6A (Typ.) multiplexing. Operating temperature range: -30 to +85 MHL/USB/UART 2paths, AUDIO 1path, Monaural Microphone 1path in 4 to 1 multiplexer. Applications Compatible with USB High Speed/Full Speed. Mobile-PhonesSmart-Phones CECBUS to ID bypass switch. Tablet-PC Audio switch handle with negative voltage signal. Digital still cameraDSC Microphone signal paths to VBUS or HDPR are built in. ID resistance support to CEA936A, Battery Charging Package W(Typ.) x D(Typ.) x H(Max.) Specification (BCS) ver1.2, MCPC, USB-OTG and UCSP75M3 3.00mm x 3.00mm x 0.85mm MHL specification. Power-On Reset. USB Charger detection support with BCS ver1.2 specification. Over voltage protection (OVP) up to 28V about VB(VBUS) input and VC(cradle) input. Power multiplexer OVP input about VB and VC. Internal Low Ron FET about OVP(VB and VC). OTG power path switch (Output side in this power path support 28V protection) is built in. VBUS linked LDO4.9V or 3.3V are selectable. 2 I C compatible Interface. ypical Application Circuit T UCSP75M3 to Charger CAP VC VOUT Ccapvc Internal Power for OTG CRADLE VC OTG VIN CAP VB USB to MIC Amplifier Ccapvb Receptacle MICOUT VB VBUS HDM1 from MHL TX- HDM2 to USB PHY HDML D- EARL from HP Amplifier from MHL TX- HDP1 HDPR D+ HDP2 to USB PHY EARR from HP Amplifier ID ID to MHL TX/USB TRX CBUS GND to Charger Internal Power for SYSTEM IO VBAT VDDIO Battery Rpu VCCIN to Host SCL Cvccin to Host SDA from System Reset RST to USB Transceiver to Host INTB VBREG to Host VCDET to Host Cvbref VBDET to Host OTG DET to Host CHG DET FACT DET to Host Fig.1 Typical Application Circuit Product structureSilicon monolithic integrated circuit This product is not designed protection against radioactive rays . www.rohm.com TSZ02201-0B2B0H300010-1-2 2012 ROHM Co., Ltd. All rights reserved. 1/24 TSZ2211114001 12.Jul.2012 Rev.001 IDSEL DSS DCDMODE USBDISEN LDOSEL GND +DatasheetDatasheet BD91411GW Contents 1.Pin Configuration .........................................................................................................................................................................3 2.Pin Description.............................................................................................................................................................................3 3.Block Diagram .............................................................................................................................................................................4 4.Absolute Maximum Ratings .........................................................................................................................................................5 5.Recommended Operating Ratings...............................................................................................................................................5 6.Electrical Characteristic ...............................................................................................................................................................6 7. Features....................................................................................................................................................................................10 7-1.Pull down resistance detection in ID pin..............................................................................................................................10 7-1-1. Priorty of MHLSW and ID detection.............................................................................................................................10 7-1-2. Application with SEND/END switch.detection..............................................................................................................10 7-1-2-1. OTG Application Detection ...................................................................................................................................10 7-1-2-2. MHL Application Detection....................................................................................................................................10 7-1-3. Enable for ID pin pull down resistance detection.........................................................................................................10 7-1-4. Retry of ID detection sequence.................................................................................................................................10 7-1-5. Polling mode of ID detection sequence.....................................................................................................................10 7-1-6. Remove ID pin pull down resistance. (Application detachment)..................................................................................10 7-2. USB port detection.............................................................................................................................................................10 7-2-1. Data Contact Detect/DCD ...........................................................................................................................................10 7-2-2. Configuration of DCD time out.....................................................................................................................................10 7-2-3. Primary Detection........................................................................................................................................................10 7-2-4. Secondary Detection ...................................................................................................................................................10 7-2-5. Shortening of second detection by Enumeration preparation......................................................................................11 7-2-6. Sequence Retrying......................................................................................................................................................11 7-2-7. Deactivation of USB por tdetection by Extarnal PIN and Internal Register..................................................................11 7-3. Signal paths .......................................................................................................................................................................11 7-3-1. HDPR/HDML Signal paths ..........................................................................................................................................11 7-3-2. Configuration of MUXSW initial path by DSS PIN.....................................................................................................11 7-3-3. Pull-down resistance in EARR/RARL pin..................................................................................................................11 7-3-4. Signal path between ID pin and CBUS pin..................................................................................................................11 7-4. Interrupt report with INTB pin...........................................................................................................................................11 7-4-1. Active level selector of INTB........................................................................................................................................11 7-4-2. Interrupt polarity...........................................................................................................................................................11 7-5. Detection of Cradle and VBUS by VBDET pin and VCDET pin..........................................................................................11 7-6. Detection of Cradle and VBUS by I2C interface reading....................................................................................................11 7-7. Detection of Over current state by I2C Interface reading.................................................................................................11 7-8. Thermal Shut down..........................................................................................................................................................11 7-9. VBREG Regulator............................................................................................................................................................11 7-10. OTG mode control............................................................................................................................................................12 7-11. VBUS signal path...........................................................................................................................................................12 7-12. Reset syetems .................................................................................................................................................................12 7-12-1. Power-On Reset........................................................................................................................................................12 7-12-2. Hardware Reset with RST.......................................................................................................................................12 7-12-3. Software reset from I2C Interface writing................................................................................................................12 2 7-13. I C Interface electrical characteristics............................................................................................................................12 2 7-14. I C Bus Interface..............................................................................................................................................................13 7-14-1. START and STOP Conditions ...................................................................................................................................13 7-14-2. Modifiynig Data..........................................................................................................................................................13 7-14-3. Acknowledge .............................................................................................................................................................14 7-14-4. Device Address .........................................................................................................................................................14 7-14-5. Write operaton...........................................................................................................................................................15 7-14-6. Address roll back specification................................................................................................................................15 7-14-7. Read back operation...............................................................................................................................................15 8.Typical Performance Curves......................................................................................................................................................16 9.Application Circuit Diagram........................................................................................................................................................17 10.I/O equivalence circuits............................................................................................................................................................18 11.Operational Notes ....................................................................................................................................................................22 12.Ordering Information................................................................................................................................................................23 13.Physical Dimension Tape and Reel Information.......................................................................................................................23 14.Marking Diagram .....................................................................................................................................................................23 15.Revision History.......................................................................................................................................................................24 www.rohm.com TSZ02201-0B2B0H300010-1-2 2012 ROHM Co., Ltd. All rights reserved. 2/24 TSZ2211115001 12.Jul.2012 Rev.001