Datasheet LVDS Interface LSI 35bit LVDS Receiver 5:35 DeSerializer BU90R104 General Description Key Specifications 2.30 to 3.60 V The BU90R104 receiver operates from 8MHz to 112MHz Supply Voltage Range 8 to 112 MHz wide clock range. Operating Frequency -40 to +85 The BU90R104 converts the LVDS serial data streams Operating Temperature Range back into 35bits of LVCMOS parallel data. Data is transmitted seven times (7X) stream and reduce the cable number by 3(1/3) or less. Packages I/O Voltage range is 2.3 to 3.6V,so it is available for many 12.0mm12.0mm1.0mm TQFP64V products. Applications Flat panel display Security camera, Digital camera Tablet Features User programmable LVCMOS data output triggering timing 5 channels of LVDS data stream are converted to 35bits by using either rising or falling edge of clock. data of parallel LVCMOS level outputs. 30bit LVDS transmitter is recommended to use BU8254KVT. 30bits of RGB output data, 5bits of timing and control output data(HSYNC, VSYNC, DE, CTL1 and CTL2) are transmitted available. Support clock frequency from 8MHz up to 112MHz. Support consumer video format including 480i, 480P, 720P and 1080i as well. Support many kinds of PC video formats such as VGA, SVGA, XGA and SXGA. Provide 784Mbps per 1ch or 3.92Gbps per device throughput rate using 112MHz clock rate. Product structureSilicon monolithic integrated circuit This product is not designed protection against radioactive rays www.rohm.co.jp TSZ02201-0L2L0H500030-1-2 2011 ROHM Co., Ltd. All rights reserved. 1/18 TSZ2211114001 27.Feb.2015 Rev.002 Datasheet BU90R104 Block Diagram LVDS Differential Input LVCMOS Output RCLK +/ + PLL CLKOUT (8112MHz) 7 Sampling Clocks 7 + RA6-RA0 RA +/ Serial to Parallel 7 + RB +/ RB6-RB0 Serial to Parallel 7 + RC6-RC0 RC +/ Serial to Parallel 7 + RD +/ RD6-RD0 Serial to Parallel 7 + RE6-RE0 RE +/ Serial to Parallel LVCMOS Input RESERVE PD OE R/F Figure 1. Block Diagram www.rohm.co.jp TSZ02201-0L2L0H500030-1-2 2011 ROHM Co., Ltd. All rights reserved. 2/18 27.Feb.2015 Rev.002 TSZ2211115001