Features Core Cortex -M3 revision 2.0 running at up to 96 MHz ARM Memory Protection Unit (MPU) Thumb -2 instruction set Memories From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank From 16 to 48 Kbytes embedded SRAM with dual banks AT91SAM 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash ARM-based controller with 4 Kbytes RAM buffer and ECC System Flash MCU Embedded voltage regulator for single supply operation POR, BOD and Watchdog for safe reset Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock. SAM3U Series High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast device startup Slow Clock Internal RC oscillator as permanent clock for device clock in low power Summary mode One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device Up to 17 peripheral DMA (PDC) channels and 4-channel central DMA Low Power Modes Sleep and Backup modes, down to 2.5 A in Backup mode Backup domain: VDDBU pin, RTC, 32 backup registers Ultra low power RTC: 0.6 A Peripherals USB 2.0 Device: 480 Mbps, 4-kbyte FIFO, up to 7 bidirectional Endpoints, dedicated DMA Up to 4 USARTs (ISO7816, IrDA , Flow Control, SPI, Manchester support) and one UART Up to 2 TWI (I2C compatible), 1 SPI, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) 3-Channel 16-bit Timer/Counter (TC) for capture, compare and PWM 4-channel 16-bit PWM (PWMC) 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features 8-channel 12-bit 1MSPS ADC with differential input mode and programmable gain stage, 8-channel 10-bit ADC I/O Up to 96 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination Three 32-bit Parallel Input/Outputs (PIO) Packages NOTE: This is a summary document. 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm The complete document is available on 100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm the Atmel website at www.atmel.com. 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm 144-ball TFBGA, 10 x 10 mm, pitch 0.8 mm 6430FSATARM10-Feb-121. SAM3U Description Atmel s SAM3U series is a member of a family of Flash microcontrollers based on the high per- formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 96 MHz and features up to 256 Kbytes of Flash and up to 52 Kbytes of SRAM. The peripheral set includes a High Speed USB Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface with NAND Flash controller, up to 4xUSARTs (SAM3U1C/2C/4C have 3), up to 2xTWIs (SAM3U1C/2C/4C have 1), up to 5xSPIs SAM3U1C/2C/4C have 4), as well as 4xPWM timers, 3xgeneral purpose 16-bit timers, an RTC, a 12-bit ADC and a 10-bit ADC. The SAM3U architecture is specifically designed to sustain high speed data transfers. It includes a multi-layer bus matrix as well as multiple SRAM banks, PDC and DMA channels that enable it to run tasks in parallel and maximize data throughput. It can operate from 1.62V to 3.6V and comes in 100-pin and 144-pin LQFP and BGA packages. The SAM3U device is particularly well suited for USB applications: data loggers, PC peripherals and any high speed bridge (USB to SDIO, USB to SPI, USB to External Bus Interface). 1.1 Configuration Summary The SAM3U series differ in memory sizes, package and features list. Table 1-1 summarizes the configurations of the six devices. Table 1-1. Configuration Summary Number FWUP, HSMCI Flash Number of Number SHDN External Bus data Device Flash Organization SRAM of PIOs USARTs of TWI pins Interface size Package ADC 8 or 16 bits, LQFP144 2x128 52 2 (8+ 8 SAM3U4E dual plane 96 4 2 Yes 4 chip selects, 8 bits Kbytes Kbytes channels) BGA144 24-bit address 8 or 16 bits, LQFP144 128 36 2 (8+ 8 SAM3U2E single plane 96 4 2 Yes 4 chip selects 8 bits Kbytes Kbytes channels) BGA144 24-bit address 8 or 16 bits, LQFP144 64 20 2 (8+ 8 SAM3U1E single plane 96 4 2 Yes 4 chip selects, 8 bits Kbytes Kbytes channels) BGA144 24-bit address 8 bits, LQFP100 2 x 128 52 2 (4+ 4 SAM3U4C dual plane 57 3 1 FWUP 2 chip selects, 4 bits Kbytes Kbytes channels) BGA100 8-bit address 8 bits, LQFP100 128 36 2 (4+ 4 SAM3U2C single plane 57 3 1 FWUP 2 chip selects, 8- 4 bits Kbytes Kbytes channels) BGA100 bit address 8 bits LQFP100 64 20 2 (4+ 4 SAM3U1C single plane 57 3 1 FWUP 2 chip selects, 4 bits Kbytes Kbytes channels) BGA100 8-bit address Note: 1. The SRAM size takes into account the 4-Kbyte RAM buffer of the NAND Flash Controller (NFC) which can be used by the core if not used by the NFC. 2 SAM3U Series 6430FSATARM10-Feb-12