Demo Board Preliminary SGDR2500P2 Product Summary Two-stage, dual-output, opto-coupled V +12 V DD gate driver evaluation board I +20/-10 A PK The SGDR2500P2 is an opto-isolated, two-stage gate driver F 100 kHz SW(MAX) optimized for high-speed hard switching of Microsemi s Duty Cycle 0-100 % APTJC120AM13VCT1AG SiC JFET half-bridge power module. The SGDR2500P2 gate driver provides isolated high-side & low- side drivers with peak output currents of +20/-10 A for fast turn-on SGDR2500P2 transients, yielding record-low switching energy losses. Features: - Suitable for driving Microsemi APTJC120AM13VCT1AG Insert Phot Here - Isolated high-side and low-side outputs - On-board derivation of isolated +/- 15 V supply voltages - Two-stage driver - switching & conduction - Peak gate current of +20/-10 A - Switching frequency up to 100 kHz - Duty cycle: 0 to 100% Schematic Overview Applications: - Hard Switched Bridge Topologies - Inverters/Converters - Product Evaluation - Research - For operation principles and intended use, refer to Application note AN-SS5. MAXIMUM RATINGS Parameter Symbol Conditions Value Unit V Positive supply voltage to GND + 12 V CC Input current logic HIGH I (high and low side inputs) 10 mA F(ON) Not connected to the JFET, + 27 I Peak Output Current output shorted to GND or pure A O - 27 capacitive load T Operating temperature + 85 C OP T Storage temperature + 100 C ST SGDR2500P2 Rev 1.3 1/4 September 2011Demo Board Preliminary SGDR2500P2 ELECTRICAL CHARACTERISTICS Value Parameter Symbol Conditions Unit Min Typ Max External Power Supplies V Positive supply voltage to GND + 11.5 +12.5 V CC without load 0.2 I Positive supply current mA CC V = +12 V, f = 100 kHz, D = 50% 1400 CC Input (characteristics same for both inputs) o V Input forward voltage I = 5 mA, T = 25 C 1.4 1.60 1.70 V F F A Input voltage, OFF V 0 - 0.8 V F(OFF) I Input current, ON 4.5 - 10 mA F(ON) o C Input capacitance V = 0V, f = 1 MHz, T = 25 C - 45 - pF in A Timing Characteristics t - 130 - ns d(ON) Delay time input to output t - 130 - ns d(OFF) Output (characteristics same for both outputs) Peak positive voltage clamped by V Output voltage - 15 - + 5V V O JFET gate-source diode R = 0.17 - + 20 GON (1) I A Peak output current O R = 0.17 - 10 - GOFF Steady-state output current I limited by R - 500 mA ODC GCOND t Output voltage rise time - - 20 ns ro t Output voltage fall time - - 20 ns fo Electrical Isolation Creep path input-output 7.6 - - mm Max V/t at V = TBD 10 kV used at 1000 Vp-p TBD kV/s Operating Conditions o T Operating Temperature 0 - + 85 C OP o T Storage Temperature 0 - + 100 ST C Notes: (1) I is limited by the JFET gate-source voltage (V ) and gate resistor (R ). Pulse width is fixed at 100 ns. Connected to PK GS G APTJC120AM13VCT1AG. SGDR2500P2 Rev 1.3 2/4 September 2011