GS1559 HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver Key Features Description The GS1559 is a reclocking Deserializer with a serial SMPTE 292M and SMPTE 259M-C compliant loop-through Cable Driver. When used in conjunction with descrambling and NRZI NRZ decoding (with bypass) the GS1574 Automatic Cable Equalizer and the DVB-ASI 8b/10b decoding GO1555/GO1525* Voltage Controlled Oscillator, a receive solution can be realized for HD-SDI, SD-SDI and DVB-ASI Auto-configuration for HD-SDI and SD-SDI applications. Serial loop-through Cable Driver output selectable as In addition to reclocking and deserializing the input data reclocked or non-reclocked stream, the GS1559 performs NRZI-to-NRZ decoding, Dual serial digital input buffers with 2 x 1 mux descrambling as per SMPTE 292M/259M-C, and word alignment when operating in SMPTE mode. When Integrated serial digital signal termination operating in DVB-ASI mode, the device will word align the Integrated Reclocker data to K28.5 sync characters and 8b/10b decode the Automatic or Manual rate selection/indication received stream. (HD/SD) Two serial digital input buffers are provided with a 2x1 Multiplexer to allow the device to select from one of two Descrambler Bypass option serial digital input signals. User selectable additional processing features The Integrated Reclocker features a very wide Input Jitter including: Tolerance of 0.3 UI (total 0.6 UI), a rapid asynchronous CRC, TRS, ANC data checksum, line number and EDH lock time, and full compliance with DVB-ASI data streams. CRC error detection and correction An integrated Cable Driver is provided for serial input Programmable ANC data detection loop-through applications and can be selected to output Illegal code remapping either buffered or reclocked data. This Cable Driver also Internal Flywheel for noise immune H, V, F extraction features an output mute on loss of signal, high-impedance FIFO load Pulse mode, adjustable signal swing, and automatic dual 20-bit/10-bit CMOS parallel output data bus slew-rate selection depending on HD/SD operational requirements. 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel The GS1559 also includes a range of data processing digital output functions such as error detection and correction, automatic Automatic standards detection and indication standards detection, and EDH support. The device can also 1.8V core Power Supply and 3.3V Charge Pump Power detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard. Supply This information is read from internal registers via the Host 3.3V digital I/O supply Interface port. JTAG test interface Line-based CRC errors, line number errors, TRS errors, EDH Available in a Pb-free package CRC errors and ancillary data checksum errors can all be detected. A single DATA ERROR pin is provided which is Small footprint (11mm x 11mm) a logical OR ing of all detectable errors. Individual error status is stored in internal ERROR STATUS registers. Applications Finally, the device can correct detected errors and insert SMPTE 292M Serial Digital Interfaces new TRS ID words, line-based CRC words, ancillary data checksum words, EDH CRC words, and line numbers. SMPTE 259M-C Serial Digital Interfaces Illegal code re-mapping is also available. All processing DVB-ASI Serial Digital Interfaces functions may be individually enabled or disabled via Host Interface control. GS1559 HD-LINX II Multi-Rate Deserializer with 1 of 71 www.gennum.com Loop-Through Cable Driver Data Sheet 30572 - 8 July 200820bit/10bit IOPROC EN/DIS FW EN/DIS JTAG/HOST F V CS TMS SCLK TCK H SDIN TDI SDOUT TDO DVB ASI smpte sync det asi sync det SMPTE BYPASS RESET TRST MASTER/SLAVE SD/HD LOCKED PCLK RC BYP CP CAP VCO VCO LB CONT LF VCO VCC VCO GND IP SEL *For new designs use the GO1555. Functional Block Diagram CD1 carrier detect CD2 rclk ctrl LOCK detect pll lock TERM 1 SMPTE De- DDI 1 scramble, Word DATA ERROR DDI 1 alignment and flywheel Reclocker CRC correct CRC check Line number S->P Line number correct DOUT 19:0 TERM 2 check TRS correct DDI 2 TRS check CSUM correct I/O Word alignment FIFO LD CSUM check EDH check & Buffer DDI 2 and ANC data correct & mux 8b/10b decode detection Illegal code re- map (o/p mute) rclk bypass pll lock CANC YANC SDO EN/DIS SDO SDO HOST Interface / JTAG Reset test RSET GS1559 Functional Block Diagram Revision History Version ECR PCN Date Changes and / or Modifications 8 147971 50711 July 2008 Changed register RASTER STRUCTURE2 from 12 bits to 13 bits in Table 4-8: Host Interface Description for Raster Structure Registers. Changed SMPTE 352 Lines from 13 to 10 in Table 4-9: Supported Video Standards. Removed references to DVB ASI in Master mode. Updated document to new format. 7 145031 May Updated description of H2 from PDBUFF GND to EQ GND in Table 1-1: Pin 2007 Descriptions. Changed GND EQ to EQ GND in 5.2 Typical Application Circuit (Part B). 6 143592 42774 January Added RoHS compliance statement to 7.3 Packaging Data. Recommended GO1555 2007 VCO for new designs. 5 140420 39452 May Corrected minor typing errors in Functional Block Diagram. Modified video format 2006 numbers for system 1125 on Table 4-4: Switch Line Position for Digital Systems. GS1559 HD-LINX II Multi-Rate Deserializer with 2 of 71 Loop-Through Cable Driver Data Sheet 30572 - 8 July 2008